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PDF DS4510U-10 Data sheet ( Hoja de datos )
| Número de pieza | DS4510U-10 | |
| Descripción | CPU Supervisor with Nonvolatile Memory and Programmable I/O | |
| Fabricantes | Maxim Integrated Products | |
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Rev 2; 8/04
CPU Supervisor with Nonvolatile Memory and
Programmable I/O
General Description
The DS4510 is a CPU supervisor with integrated 64-
byte EEPROM memory and four programmable, non-
volatile (NV) I/O pins. It is configured with an
industry-standard I2C™ interface using either fast-
mode (400kbps) or standard-mode (100kbps) commu-
nication. The I/O pins can be used as general-purpose
I2C-to-parallel I/O expander with unlimited read/write
capability. EEPROM registers allow the power-on value
of the I/O pins to be adjusted to keep track of the sys-
tem’s state through power cycles, and the CPU supervi-
sor’s timer can be adjusted between 125ms and
1000ms to meet most any application need.
Features
♦ Accurate 5%, 10%, or 15% 5V Power-Supply
Monitoring
♦ Programmable Reset Timer Maintains Reset After
VCC Returns to an In-Tolerance Condition
♦ Four Programmable, NV, Digital I/O Pins with
Selectable Internal Pullup Resistor
♦ 64 Bytes of User EEPROM
♦ Reduces Need for Discrete Components
♦ I2C-Compatible Serial Interface
♦ 10-Pin µSOP Package
Applications
RAM-Based FPGA Bank Switching for
Multiple Profiles
Industrial Controls
Cellular Telephones
PC Peripherals
PDAs
Ordering Information
PART
DS4510U-5
DS4510U-10
DS4510U-15
DS4510U-5/T&R
DS4510U-10/T&R
DS4510U-15/T&R
VCC TRIP
POINT
TEMP RANGE
PIN-
PACKAGE
5% -40°C to +85°C 10 µSOP
10% -40°C to +85°C 10 µSOP
15% -40°C to +85°C 10 µSOP
5% -40°C to +85°C 10 µSOP
10% -40°C to +85°C 10 µSOP
15% -40°C to +85°C 10 µSOP
Pin Configuration
TOP VIEW
A0 1
SDA 2
SCL 3
VCC 4
GND 5
DS4510
µSOP
10 RST
9 I/O0
8 I/O1
7 I/O2
6 I/O3
Typical Operating Circuit
2.7V TO 5.5V
4.7kΩ
FROM
SYSTEM
CONTROLLER
4.7kΩ
A0
SDA
SCL
VCC
DS4510
GND
4.7kΩ
RST RESET VCC
I/O0 CONFIG0
I/O1 CONFIG1 FPGA
I/O2 CONFIG2
I/O3 CONFIG3
GND
I2C is a registered trademark of Philips Corp. Purchase of I2C components of Maxim Integrated Products, Inc. or one of its
Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
the system conforms to the I2C Standard Specifications as defined by Philips.
______________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
CPU Supervisor with Nonvolatile Memory and
Programmable I/O
Typical Operating Characteristics (continued)
(VCC = +5.0V, TA = +25°C, unless otherwise noted.)
VCC TRIP POINT vs. TEMPERATURE
5.0
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4.0
-40 -20
0 20 40 60
TEMPERATURE (°C)
80
RST OUTPUT VOLTAGE vs. SUPPLY VOLTAGE
6.0
5.5 5.6kΩ PULLUP
5.0 RESISTOR ON RST
4.5 SDA = SCL = VCC
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
I/O PULLUP RESISTANCE vs. TEMPERATURE
5.25
5.20
5.15
5.10
5.05
5.00
4.95
4.90
4.85
4.80
4.75
-40 -20
0 20 40 60
TEMPERATURE (°C)
80
Pin Description
PIN NAME
FUNCTION
1
A0
I2C Address Input. This input pin determines the chip address of the device. A0 = 0 sets the slave
address to 1010000b, A0 = 1 sets the slave address to 1010001b.
2
SDA
Serial Data Input/Output. Bidirectional I2C data pin.
3 SCL Serial Clock Input. I2C clock input.
4 VCC Power Input
5
GND
Ground
6 I/O3 Input/Output 3. I2C accessible bidirectional I/O pin.
7 I/O2 Input/Output 2. I2C accessible bidirectional I/O pin.
8 I/O1 Input/Output 1. I2C accessible bidirectional I/O pin.
9 I/O0 Input/Output 0. I2C accessible bidirectional I/O pin.
10 RST Active-Low Reset Output. Open-drain CPU supervisor reset output.
_____________________________________________________________________ 5
5 Page 
CPU Supervisor with Nonvolatile Memory and
Programmable I/O
dition, write the slave address (R/W = 0), and the first
memory address of the next page before continuing to
write data.
Acknowledge Polling: Any time an EEPROM page is
written, the DS4510 requires the EEPROM write time
(tW) after the stop condition to write the contents of the
page to EEPROM. During the EEPROM write time, the
DS4510 does not acknowledge its slave address
because it is busy. It is possible to take advantage of
that phenomenon by repeated addressing the DS4510,
which allows the next page to be written as soon as the
DS4510 is ready to receive the data. The alternative to
acknowledge polling is to wait for maximum period of
tW to elapse before attempting to write again to the
DS4510.
EEPROM Write Cycles: When EEPROM writes occur,
the DS4510 writes the whole EEPROM memory page
even if only a single byte on the page was modified.
Writes that do not modify all 8 bytes on the page are
allowed and do not corrupt the remaining bytes of
memory on the same page. Because the whole page is
written, bytes on the page that were not modified dur-
ing the transaction are still subject to a write cycle. This
can result in a whole page being worn out over time by
writing a single byte repeatedly. Writing a page one
byte at a time wears the EEPROM out eight times faster
than writing the entire page at once. The DS4510’s
EEPROM memory is guaranteed to handle 50,000 write
cycles at +70°C. Writing to SEEPROM memory with
SEE = 1 does not count as an EEPROM write cycle
when evaluating the EEPROM’s estimated lifetime.
Reading a Single Byte from a Slave: Unlike the write
operation that uses the memory address byte to define
where the data is to be written, the read operation
occurs at the present value of the memory address
counter. To read a single byte from the slave the mas-
ter generates a start condition, writes the slave address
with R/W = 1, reads the data byte with a NACK to indi-
cate the end of the transfer, and generates a stop con-
dition.
Manipulating the Address Counter for Reads: A
dummy write cycle can be used to force the address
counter to a particular value. To do this the master gen-
erates a start condition, writes the slave address (R/W
= 0), writes the memory address where it desires to
read, generates a repeated start condition, writes the
slave address (R/W = 1), reads data with ACK or NACK
as applicable, and generates a stop condition.
See Figure 7 for a read example using the repeated
start condition dummy write cycle.
Reading Multiple Bytes from a Slave: The read oper-
ation can be used to read multiple bytes with a single
transfer. When reading bytes from the slave, the master
simply ACKs the data byte if it desires to read another
byte before terminating the transaction. After the mas-
ter reads the last byte it NACKs to indicate the end of
the transfer and generates a stop condition. This can
be done with or without modifying the address
counter’s location before the read cycle. The DS4510
does not wrap on page boundaries during read opera-
tions, but the counter rolls from its upper-most memory
address FFh to 00h if the last memory location is read
during the read transaction.
Example: The entire memory contents of the DS4510
can be read with a single transfer starting at address
F0h that reads 80 bytes of data. Addresses F0h to FFh
are read sequentially, the address counter rolls to 00h,
and then addresses 00h to 3Fh can be read sequential-
ly. This allows the entire memory contents to be read in
a single operation without reading the undefined con-
tents of the reserved area of the memory.
Application Information
Advantages of Using the SEE Bit to Disable
EEPROM Writes
The SEE bit allows EEPROM writes to be disabled for
the SRAM-shadowed EEPROM bytes, allowing the
SRAM of SEE registers to change without writing the
EEPROM to the same value. This prevents write opera-
tions from changing the power-on value of the I/O pins,
reduces the number of EEPROM write cycles, and
speeds up I/O operations because the DS4510 does
not require an internally timed EEPROM write cycle to
complete the operation.
Power-Supply Decoupling
To achieve the best results when using the DS4510,
decouple the power supply with a 0.01µF or a 0.1µF
capacitor. Use high-quality, ceramic, surface-mount
capacitors, and mount the capacitors as close as pos-
sible to the VCC and GND pins of the DS4510 to mini-
mize lead inductance.
SDA and SCL Pullup Resistors
SDA is an open-collector output on the DS4510 that
requires a pullup resistor to realize high logic levels.
Because the DS4510 does not utilize clock cycle
stretching, a master using either an open-collector out-
put with a pullup resistor or a normal output driver can
be utilized for SCL. Pullup resistor values should be
chosen to ensure that the rise and fall times listed in the
AC Electrical Characteristics are within specification.
____________________________________________________________________ 11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet DS4510U-10.PDF ] | |
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