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PDF DS3886AVF Data sheet ( Hoja de datos )

Número de pieza DS3886AVF
Descripción BTL 9-Bit Latching Data Transceiver
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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June 1998
DS3886A
BTL 9-Bit Latching Data Transceiver
General Description
The DS3886A is a higher speed, lower power, pin compat-
ible version of the DS3886.
The DS3886A is one in a series of transceivers designed
specifically for the implementation of high performance Fu-
turebus+ and proprietary bus interfaces. The DS3886A is a
BTL 9-Bit Latching Data Transceiver designed to conform to
IEEE 1194.1 (Backplane Transceiver Logic — BTL) as speci-
fied in the IEEE 896.2 Futurebus+ specification. The
DS3886A incorporates an edge-triggered latch in the driver
path which can be bypassed during fall-through mode of op-
eration and a transparent latch in the receiver path. Utiliza-
tion of the DS3886A simplifies the implementation of byte
wide address/data with parity lines and also may be used for
the Futurebus+ status, tag and command lines.
The DS3886A driver output configuration is an NPN open
collector which allows Wired-OR connection on the bus.
Each driver output incorporates a Schottky diode in series
with it’s collector to isolate the transistor output capacitance
from the bus, thus reducing the bus loading in the inactive
state. The combined output capacitance of the driver output
and receiver input is less than 5 pF. The driver also has high
sink current capability to comply with the bus loading re-
quirements defined within IEEE 1194.1 BTL specification.
Backplane Transceiver Logic (BTL) is a signaling standard
that was invented and first introduced by National Semicon-
ductor, then developed by the IEEE to enhance the perfor-
mance of backplane buses. BTL compatible transceivers
feature low output capacitance drivers to minimize bus load-
ing, a 1V nominal signal swing for reduced power consump-
tion and receivers with precision thresholds for maximum
noise immunity. The BTL standard eliminates settling time
delays that severely limit TTL bus performance, and thus
provide significantly higher bus transfer rates. The back-
plane bus is intended to be operated with termination resis-
tors (selected to match the bus impedance) connected to
2.1V at both ends. The low voltage is typically 1V.
Separate ground pins are provided for each BTL output to
minimize induced ground noise during simultaneous switch-
ing.
The unique driver circuitry meets the maximum slew rate of
0.5 V/ns which allows controlled rise and fall times to reduce
noise coupling to adjacent lines.
The transceiver’s high impedance control and driver inputs
are fully TTL compatible.
The receiver is a high speed comparator that utilizes a Band-
gap reference for precision threshold control, allowing maxi-
mum noise immunity to the BTL 1V signaling level. Separate
QVCC and QGND pins are provided to minimize the effects
of high current switching noise. The output is TRI-STATE®
and fully TTL compatible.
The DS3886A supports live insertion as defined in IEEE
896.2 through the LI (Live Insertion) pin. To implement live
insertion the LI pin should be connected to the live insertion
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
power connector. If this function is not supported, the LI pin
must be tied to the VCC pin. The DS3886A also provides
glitch free power up/down protection during power sequenc-
ing.
The DS3886A has two types of power connections in addi-
tion to the LI pin. They are the Logic VCC (VCC) and the Quiet
VCC (QVCC). There are two Logic VCC pins on the DS3886A
that provide the supply voltage for the logic and control cir-
cuitry. Multiple connections are provided to reduce the ef-
fects of package inductance and thereby minimize switching
noise. As these pins are common to the VCC bus internal to
the device, a voltage delta should never exist between these
pins and the voltage difference between V CC and QVCC
should never exceed ±0.5V because of ESD circuitry.
When CD (Chip Disable) is high, An is in high impedance
state and Bn is high. To transmit data (An to Bn) the T/R sig-
nal is high.
When RBYP is high, the positive edge triggered flip-flop is in
the transparent mode. When RBYP is low, the positive edge
of the ACLK signal clocks the data.
In addition, the ESD circuitry between the VCC pins and all
other pins except for BTL I/O’s and LI pins requires that any
voltage on these pins should not exceed the voltage on VCC
+0.5V.
There are three different types of ground pins on the
DS3886A; the logic ground (GND), BTL grounds
(B0GND–B8GND) and the Bandgap reference ground
(QGND). All of these ground reference pins are isolated
within the chip to minimize the effects of high current switch-
ing transients. For optimum performance the QGND should
be returned to the connector through a quiet channel that
does not carry transient switching current. The GND and
B0GND–B8GND should be connected to the nearest back-
plane ground pin with the shortest possible path.
Since many different grounding schemes could be imple-
mented and ESD circuitry exists on the DS3886A, it is impor-
tant to note that any voltage difference between ground pins,
QGND, GND or B0GND–B8GND should not exceed ±0.5V
including power up/down sequencing.
The DS3886A is offered in 44-pin PLCC, and 44-pin PQFP
high density package styles.
Features
n Fast propagation delay (3ns typ)
n 9-BIT BTL Latched Transceiver
n Driver incorporates edge triggered latches
n Receiver incorporates transparent latches
n Meets IEEE 1194.1 Standard on Backplane Transceiver
Logic (BTL)
n Supports Live Insertion
n Glitch free Power-up/down protection
n Typically less than 5 pF Bus-port capacitance
n Low Bus-port voltage swing (typically 1V) at 80 mA
© 1999 National Semiconductor Corporation DS011458
www.national.com

1 page




DS3886AVF pdf
AC Electrical Characteristics (Note 5) (Continued)
TA = 0˚C to +70˚C, VCC = 5V ±10%
Symbol
Parameter
Conditions
Min Typ Max Units
RECEIVER
tPLZ
tPZL
CD to An
Disable Time
Enable Time
LE = 3.0V
Bn = 2.1V, T/R = 0V
(Figure 8 and Figure 9)
3 5 10 ns
2.5 6 8 ns
tPHZ
Disable Time
LE = 3.0V
4 6 8.5 ns
tPZH
Enable Time
Bn = 1.1V, T/R = 0V
2.5 5 8.5 ns
(Figure 8 and Figure 9)
tPLZ
tPZL
tPHZ
tPZH
T/R to An
Disable Time
Enable Time
Disable Time
Enable Time
LE = 3.0V, Bn = 2.1V
CD = 0V (Figure 10 and Figure 11)
LE = 3.0V
Bn = 1.1V, CD = 0V
(Figure 8 and Figure 9)
3 7.5 12
5 9.5 15
36 9
36 9
ns
ns
ns
ns
tskew
LE to An
Bn to An
Same Package
Same Package
(Note 7)
(Note 7)
0.5 3
0.5 2.5
ns
ns
RECEIVER TIMING REQUIREMENTS (Figure 7)
tS Bn to LE
Set-up Time
tH LE to Bn
Hold Time
tpw LE Pulse Width
PARAMETERS NOT TESTED
CD = T/R = 0V
CD = T/R = 0V
CD = T/R = 0V
3 ns
1 ns
5 ns
Coutput Capacitance at Bn
(Note 8)
tNR Noise Rejection
(Note 9)
Note 6: Input waveforms shall have a rise and fall time of 3 ns.
5 pF
1 ns
Note 7: tskew is an absolute value defined as differences seen in propagation delay between drivers in the same package with identical load conditions.
Note 8: The parameter is tested using TDR techniques described in P1194.0 BTL Backplane Design Guide.
Note 9: This parameter is tested during device characterization. The measurements revealed that the part will typically reject 1 ns pulse width.
Note 10: Futurebus+ transceivers are required to limit bus signal rise and fall times to no faster than 0.5 V/ns, measured between 1.3V and 1.8V (approximately 20%
to 80% of nominal voltage swing). The rise and fall times are measured with a transceiver loading equivalent to 12.5tied to +2.1 V DC.
Pin Description
Pin Name
Number of Input/
Description
Pins
Output
A0–A8
9 I/O TTL TRI-STATE receiver output and driver input
ACLK
1 I Clock input for latch
B0–B8
9 I/O BTL receiver input and driver output
B0GND–B8GND
9
NA Driver output ground reduces ground bounce due to high current switching of
driver outputs. (Note 11)
CD 1 I Chip Disable
GND
2 NA Ground reference for switching circuits.(Note 10)
LE 1 I Latch Enable
LI 1 NA Power supply for live insertion. Boards that require live insertion should connect
LI to the live insertion pin on the connector. (Note 12)
NC 5 NA No Connect
QGND
1 NA Ground reference for receiver input bandgap reference and non-switching
circuits. (Note 11)
QVCC
RBYP
1 NA VCC supply for bandgap reference and non-switching circuits. (Note 12)
1 I Register bypass enable
T/R 1 I Transmit/Receive — Transmit (An to Bn) Receive (Bn to An)
VCC 2 NA VCC supply for switching circuits. (Note 12)
Note 11: The multiplicity of grounds reduces the effective inductance of bonding wires and leads, which then reduces the noise caused by transients on the ground
path. The various ground pins can be tied together provided that the external ground has low iductance (i.e., ground plane with power pins and many signal pins con-
5 www.national.com

5 Page





DS3886AVF arduino
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Note: All dimensions in millimeters
44-Lead Plastic Quad Flatpak
Order Number DS3886AVF
NS Package Number VF44B
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
www.national.com
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Fax: 65-2504466
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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