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PDF DS3884A Data sheet ( Hoja de datos )
| Número de pieza | DS3884A | |
| Descripción | BTL Handshake Transceiver | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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August 2000
DS3884A
BTL Handshake Transceiver
General Description
The DS3884A is one in a series of transceivers designed
specifically for the implementation of high performance Fu-
turebus+ and proprietary bus interfaces. The DS3884A is a
BTL 6-bit Handshake Transceiver designed to conform to
IEEE 1194.1 (Backplane Transceiver Logic — BTL) as speci-
fied in the IEEE 896.2 Futurebus+ specification.
Features
n Fast propagation delay (3 ns typ)
n 6-bit BTL transceiver
n Selective receiver glitch filtering (FR1–FR3)
n Meets 1194.1 Standard on Backplane Transceiver Logic
(BTL)
n Supports live insertion
n Glitch free power-up/down protection
n Typically less than 5 pF bus-port capacitance
n Low Bus-port voltage swing (typically 1V) at 80 mA
n TTL compatible driver and control inputs
n Separate TTL I/O
n Open collector bus-port outputs allow Wired-OR
connection
n Controlled rise and fall time to reduce noise coupling to
adjacent lines
n Built in Bandgap reference with separate QV CC and
QGND pins for precise receiver thresholds
n Exceeds 2 kV ESD testing (Human Body Model)
n Individual Bus-port ground pins
n Product offered in PQFP package styles
Connection Diagram
Order Number DS3884AVF
See NS Package VF44B
DS011460-1
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation DS011460
www.national.com
1 page  
Pin Descriptions
Pin Name
Number of
Input/
Description
Pins
Output
B1–B6
6 I/O BTL receiver input and driver output
B1GND–B6GND
6
NA Driver output ground reduces bounce due to high
current switching of driver outputs
(Note 12)
DE* 1 I Driver Enable Low
D1–D6
6 I TTL Driver Input
FR1–FR3
3 O TTL Filtered Receiver Output
GND
3 NA Ground reference for switching circuits.
(Note 12)
LI 1 NA Power supply for live insertion. Boards that require live
insertion should connect LI to the live insertion pin on
the connector. (Note 13)
NC 4 NA No Connect
PS1, PS2
2 I Pulse Width Selection pin determines glitch filter setting
(Note 14)
R1–R6
6 O TTL Receiver Output
REXT
1 NA External Resistor pin. External resistor is used for
internal biasing of filter circuitry. The 13 kΩ resistor shall
be connected between REXT and GND. The resistor
shall have a tolerance of 1% and a temperature
coefficient of 100 ppm/˚C or better.
QGND
2 NA Ground reference for receiver input bandgap reference
and non-switching circuits (Note 12)
QVCC
1 NA VCC supply for bandgap reference and non-switching
circuits (Note 13)
VCC 2 NA VCC supply for switching circuits (Note 13)
Note 12: the multiplicity of grounds reduces the effective inductance of bonding wires and leads, which then reduces the noise caused by transients on the ground
path. The various ground pins can be tied together provided that the external ground has low inductance (i.e., ground plane with power pins and many signal pins
connected to the backplane ground). If the external ground floats considerably during transients, precautionary steps should be taken to prevent QGND from moving
with reference to the backplane ground. The receiver threshold should have the same ground reference as the signal coming from the backplane. A voltage offset
between their grounds will degrade the noise margin.
Note 13: The same considerations for ground are used for V CC in reducing lead inductance (see Note 12). QVCC and V CC should be tied together externally. If live
insertion is not supported, the LI pin can be tied together with QVCC and VCC.
Note 14: See AC characteristics for filter setting.
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