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PDF DS36C280TN Data sheet ( Hoja de datos )

Número de pieza DS36C280TN
Descripción Slew Rate Controlled CMOS EIA-RS-485 Transceiver
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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No Preview Available ! DS36C280TN Hoja de datos, Descripción, Manual

July 1998
DS36C280
Slew Rate Controlled CMOS EIA-RS-485 Transceiver
General Description
The DS36C280 is a low power differential bus/line trans-
ceiver designed to meet the requirements of RS-485 Stan-
dard for multipoint data transmission. In addition, it is com-
patible with TIA/EIA-422-B.
The slew rate control feature allows the user to set the driver
rise and fall times by using an external resistor. Controlled
edge rates can reduce switching EMI.
The CMOS design offers significant power savings over its
bipolar and ALS counterparts without sacrificing ruggedness
against ESD damage. The device is ideal for use in battery
powered or power conscious applications. ICC is specified at
500 µA maximum.
The driver and receiver outputs feature TRI-STATE® capabil-
ity. The driver outputs operate over the entire common mode
range of −7V to +12V. Bus contention or fault situations are
handled by a thermal shutdown circuit, which forces the
driver outputs into the high impedance state.
The receiver incorporates a fail safe circuit which guarantees
a high output state when the inputs are left open (Note 1) .
Features
n 100% RS-485 compliant
— Guaranteed RS-485 device interoperation
n Low power CMOS design: ICC 500 µA max
n Adjustable slew rate control
— Minimizes EMI affects
n Built-in power up/down glitch-free circuitry
— Permits live transceiver insertion/displacement
n DIP and SOIC packages available
n Industrial temperature range: −40˚C to +85˚C
n On-board thermal shutdown circuitry
— Prevents damage to the device in the event of
excessive power dissipation
n Wide common mode range: −7V to +12V
n Receiver open input fail-safe (Note 1)
n 14 unit load (DS36C280): 128 nodes
n 12 unit load (DS36C280T): 64 nodes
n ESD (human body model): 2 kV
Connection and Logic Diagram
DS012052-1
Order Number DS36C280TM, DS36C280TN
DS36C280M and DS36C280N
See NS Package Number M08A or N08E
Truth Table
DRIVER SECTION
DE/RE* DI DO/RI
H HH
H LL
L XZ
RECEIVER SECTION
DE/RE*
RI-RI*
L +0.2V
L −0.2V
HX
L OPEN (Note 1)
Note 1: Non-terminated, Open Inputs only
DO*/RI*
L
H
Z
RO
H
L
Z
H
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS012052
www.national.com

1 page




DS36C280TN pdf
Parameter Measurement
Information (Continued)
DS012052-8
FIGURE 8. TRI-STATE Waveforms (tPZH, tPHZ)
DS012052-10
FIGURE 10. TRI-STATE Waveforms (tPZL, tPLZ)
DS012052-9
FIGURE 9. TRI-STATE Test Circuit (tPZL, tPLZ)
DS012052-11
FIGURE 11. Receiver VOH and VOL
DS012052-12
FIGURE 12. Receiver Differential
Propagation Delay Test Circuit
DS012052-13
FIGURE 13. Receiver Differential Propagation Delay Waveforms
FIGURE 14. Receiver TRI-STATE Test Circuit
DS012052-14
5 www.national.com

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