|
|
PDF DS33Z44 Data sheet ( Hoja de datos )
| Número de pieza | DS33Z44 | |
| Descripción | Quad Ethernet Mapper | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de DS33Z44 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
www.maxim-ic.com
GENERAL DESCRIPTION
The DS33Z44 extends four 10/100 Ethernet LAN
segments by encapsulating MAC frames in HDLC or
X.86 (LAPS) for transmission over four PDH/TDM
data streams. The serial links support bidirectional
synchronous interconnect up to 52Mbps over xDSL,
T1/E1/J1, T3/E3, V.35/Optical, OC-1/EC-1, or
SONET/SDH Tributary.
The device performs store-and-forward of packets
with full wire-speed transport capability. The built-in
Committed Information Rate (CIR) controllers
provide fractional bandwidth allocation up to the line
rate in increments of 512kbps. The DS33Z44 can
operate with an inexpensive external processor,
EEPROM or in a stand-alone hardware mode.
APPLICATIONS
Transparent LAN Service
LAN Extension
Ethernet Delivery Over T1/E1/J1, T3/E3,
OC-1/EC-1, G.SHDSL, or HDSL2/4
FUNCTIONAL DIAGRAM
4 SERIAL
PORTS
DS33Z44
TRANSCEIVERS/
SERIAL DRIVERS
BERT
HDLC/X.86
MAPPER
CONFIG.
LOADER
PROM
OR mC
SDRAM
DS33Z44
Quad Ethernet Mapper
FEATURES
§ Four 10/100 IEEE 802.3 Ethernet MACs (MII and
RMII) Half/Full Duplex with Automatic Flow
Control
§ Four 52Mbps Synchronous TDM Serial Ports
with independent transmit and receive timing.
§ HDLC/LAPS Encapsulation with Programmable
FCS and Interframe Fill
§ Committed Information Rate Controllers Provide
Fractional Allocations in 512kbps Increments
§ Programmable BERT for Serial (TDM) Interfaces
§ External 16MB, 100MHz SDRAM Buffering
§ Parallel Microprocessor Interface
§ SPI Interface and Hardware Mode for Operation
Without a Host Processor
§ 1.8V Operation with 3.3V Tolerant I/O
§ IEEE 1149.1 JTAG Support
Features Continued on Page 10.
ORDERING INFORMATION
PART
TEMP RANGE PIN-PACKAGE
DS33Z44
-40°C to +85°C 256 CSBGA
Go to www.maxim-ic.com/telecom for a complete list of
Telecommunications data sheets, evaluation kits, application
notes, and software downloads.
4 10/100
MACs
4 MII/RMII
4 10/100
ETHERNET
PHYs
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
1 of 181
REV: 120304
1 page  
DS33Z44 Quad Ethernet Mapper
12.2.5 HIGHZ ...............................................................................................................................................178
12.2.6 IDCODE ............................................................................................................................................178
12.3 JTAG ID CODES .................................................................................................................... 179
12.4 TEST REGISTERS.................................................................................................................... 179
12.5 BOUNDARY SCAN REGISTER ................................................................................................... 179
12.6 BYPASS REGISTER ................................................................................................................. 179
12.7 IDENTIFICATION REGISTER ...................................................................................................... 179
12.8 JTAG FUNCTIONAL TIMING ..................................................................................................... 180
13 PACKAGE INFORMATION.............................................................................................181
13.1 17MM X 17MM 256-CSBGA .................................................................................................... 181
5 of 181
5 Page 
DS33Z44 Quad Ethernet Mapper
2.6 SDRAM Interface
· Interface for 128-Mbit, 32-bit-wide SDRAM
· SDRAM Interface speed up to 100 MHz
· Auto refresh timing
· Automatic precharge
· Master clock provided to the SDRAM
· No external components required for SDRAM connectivity
2.7 MAC Interfaces
· Four MAC ports with standard MII (less TX_ER) or RMII
· 10Mbps and 100 Mbps data rates
· Configurable DTE or DCE modes
· Facilitates auto-negotiation by host microprocessor
· Programmable half and full-duplex modes
· Flow control for both half-duplex (back-pressure) and full-duplex (PAUSE) modes
· Programmable maximum MAC frame size up to 2016 bytes
· Minimum MAC frame size: 64 bytes
· Discards frames greater than programmed maximum MAC frame size and runt, non-octet bounded,
or bad-FCS frames upon reception
· Configurable for promiscuous broadcast-discard mode.
· Programmable threshold for SDRAM queues to initiate flow control and status indication
· MAC loopback support for transmit data looped to receive data at the MII/RMII interface
2.8 Microprocessor Interface
· 8-bit data bus
· Non-multiplexed Intel and Motorola Timing Modes
· Internal software reset and External Hardware reset input pin
· Global interrupt output pin
2.9 Serial SPI Interface—Master Mode Only
· Provides chip select and clock for external EEPROM
· Operation up to 8.33 MHz
· 4-signal interface
2.10 Default Configurations
· Three default hardware configurations for operation without an external microprocessor
· Hardware modes set for easy connection to T1/E1 and T3/E3 WAN Systems
· Hardware pins provide some flexibility for configuration
2.11 Test and Diagnostics
· IEEE 1149.1 support
· Programmable on-chip BERT
· Patterns include pseudorandom QRSS, Daly, and user-defined repetitive patterns
· Loopbacks (remote, local, analog, and per-channel loopback)
11 of 181
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DS33Z44.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DS33Z44 | Quad Ethernet Mapper | Maxim Integrated Products |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |