|
|
PDF DS3134 Data sheet ( Hoja de datos )
| Número de pieza | DS3134 | |
| Descripción | Chateau Channelized T1 And E1 And HDLC Controller | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de DS3134 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
PRELIMINARY
DS3134
Chateau – Channelized T1 And
E1 And HDLC Controller
www.dalsemi.com
FEATURES
• 256 Channel HDLC Controller that Supports
up to 64 T1 or E1 Lines or Two T3 Lines
• 256 Independent bi-directional HDLC
channels
• 16 physical ports (16 Tx & 16 Rx) that can
be configured as either channelized or
unchannelized
• Two fast (52 Mbps) ports/other ports capable
of speeds up to 10 Mbps (unchannelized)
• Channelized Ports 0 to 15 handle one, two or
four T1 or E1 lines
• Supports up to 64 T1 or E1 data streams
• Per channel DS0 loopbacks in both direction
• Support transparent Mode
• V.54 loopback code detector
• Onboard Bit Error Rate Tester (BERT) with
auto error insertion capability
• BERT function can be assigned to any
HDLC channel or any port
• 104 Mbps full duplex throughput
• Large 16 kbits FIFO in both receive and
transmit directions
• Efficient scatter / gather DMA
• Receive data packets are Time stamped
• Transmit packet priority setting
• Local bus allows for PCI bridging or local
access
• Intel or Motorola bus signals supported
• 25 MHz to 33 MHz 32-bit PCI (V2.1)
backplane interface
• 3.3V low power CMOS with 5V tolerant I/O
• JTAG support IEEE 1149.1
• 256 Lead Plastic BGA (27 mm x 27 mm)
DESCRIPTION
The DS3134 Chateau device is a 256-channel HDLC controller. The DS3134 is capable of handling up to
64 T1 or E1 data streams or 2 T3 data streams. Each of the 16 physical ports can handle one, two or four
T1 or E1 data streams. The Chateau consists of the following blocks:
• Layer Block
• HDLC Block
• FIFO Block
• DMA Block
• PCI Bus
• Local Bus
1 of 203
101600
1 page  
TABLE OF CONTENTS
DS3134
Section 1: Introduction……………………………………………………………………………………..7
Section 2: Signal Description…………………………………………………………………………… 16
2.1 Overview / Signal Lead List………………………………………………………………… 16
2.2 Serial Port Interface Signal Description…………………………………………………… 22
2.3 Local Bus Signal Description………………………………………………………………. 24
2.4 JTAG Signal Description…………………………………………………………………… 27
2.5 PCI Bus Signal Description………………………………………………………………… 28
2.6 Supply & Test Signal Description…………………...…………………………………….. 31
Section 3: Memory Map………………………………………………………………………………… 32
3.0 Introduction………………………………………………………………………………….. 32
3.1 General Configuration Registers………………………………………………………….. 32
3.2 Receive Port Registers…………………………………………………………………….. 33
3.3 Transmit Port Registers……………………………………………………………………. 33
3.4 Channelized Port Registers……………………………………………………………….. 34
3.5 HDLC Registers……………………………………………………………………………. 35
3.6 BERT Registers…………………………………………………………………………….. 35
3.7 Receive DMA Registers……………………………………………………………………. 35
3.8 Transmit DMA Registers…………………………………………………………………… 36
3.9 FIFO Registers……………………………………………………………………………… 36
3.10 PCI Configuration Registers for Function 0……………………………………………. 36
3.11 PCI Configuration Registers for Function 1……………………………………………. 37
Section 4: General Device Configuration & Status/Interrupt………………………………………….. 37
4.1 Master Reset & ID Register Description…………………………………………………. 37
4.2 Master Configuration Register Description………………………………………………. 38
4.3 Status & Interrupt…………………………………………………………………………… 40
4.3.1 Status & Interrupt General Description……………………………………… 40
4.3.2 Status & Interrupt Register Description……………………………………… 43
4.4 Test Register Description………………………………………………………………….. 50
Section 5: Layer One…………………………………………………………………………………… 51
5.1 General Description………………………………………………………………………… 51
5.2 Port Register Description………………………………………………………………….. 55
5.3 Layer One Configuration Register Description………………………………………….. 59
5.4 Receive V.54 Detector…………………………………………………………………….. 65
5.5 BERT…………………………………………………………………………………………69
5.6 BERT Register Description……………………………………………………………….. 70
Section 6: HDLC………………………………………………………………………………………… 77
6.1 General Description……………………………………………………………………….. 77
6.2 HDLC Register Description………………………………………………………………. 79
5 of 203
5 Page 
DS3134
In the receive path, the following process occurs. The HDLC Engines collect the incoming data into
32-bit dwords and then signal the FIFO that the engine has data to transfer to the FIFO. The 16 ports are
priority decoded (Port 0 gets the highest priority) for the transfer of data from the HDLC Engines to the
FIFO Block. Please note that in a channelized application, a single port may contain up to 128 HDLC
channels and since HDLC channel numbers can be assigned randomly, the HDLC channel number has no
bearing on the priority of this data transfer. This situation is of no real concern however since the
DS3134 has been designed to handle up to 104 Mbps in both the receive and transmit directions without
any potential loss of data due to priority conflicts in the transfer of data from the HDLC Engines to the
FIFO and vice versa.
The FIFO transfers data from the HDLC Engines into the FIFO and checks to see if the FIFO has filled to
beyond the programmable High Water Mark. If it has, then the FIFO signals to the DMA that data is
ready to be burst read from the FIFO to the PCI Bus. The FIFO Block controls the DMA Block and it
tells the DMA when to transfer data from the FIFO to the PCI Bus. Since the DS3134 can handle
multiple HDLC channels, it is quite possible that at any one time, several HDLC channels will need to
have data transferred from the FIFO to the PCI Bus. The FIFO determines which HDLC channel the
DMA will handle next via a Host configurable algorithm, which allows the selection to be either round
robin or priority, decoded (with HDLC Channel 1 getting the highest priority). Depending on the
application, the selection of this algorithm can be quite important. The DS3134 cannot control when it
will be granted PCI Bus access and if bus access is restricted, then the Host may wish to prioritize which
HDLC channels get top priority access to the PCI Bus when it is granted to the DS3134.
When the DMA transfers data from the FIFO to the PCI Bus, it burst reads all available data in the FIFO
(even if the FIFO contains multiple HDLC packets) and tries to empty the FIFO. If an incoming HDLC
packet is not large enough to fill the FIFO to the High Water Mark, then the FIFO will not wait for more
data to enter the FIFO, it will signal the DMA that a End Of Frame (EOF) was detected and that data is
ready to be transferred from the FIFO to the PCI Bus by the DMA.
In the transmit path, a very similar process occurs. As soon as a HDLC channel is enabled, the HDLC
(Layer 2) Engines begin requesting data from the FIFO. Like the receive side, the 16 ports are priority
decoded with Port 0 getting the highest priority. Hence, if multiple ports are requesting packet data, the
FIFO will first satisfy the requirements on all the enabled HDLC channels in the lower numbered ports
before moving on to the higher numbered ports. Again there is no potential loss of data as long as the
transmit throughput maximum of 104 Mbps is not exceeded. When the FIFO detects that a HDLC Engine
needs data, it then transfers the data from the FIFO to the HDLC Engines in 8-bit chunks. If the FIFO
detects that the FIFO is below the Low Water Mark, it then checks with the DMA to see if there is any
data available for that HDLC Channel. The DMA will know if any data is available because the Host on
the PCI Bus will have informed it of such via the Pending Queue Descriptor. When the DMA detects that
data is available, it informs the FIFO and then the FIFO decides which HDLC channel gets the highest
priority to the DMA to transfer data from the PCI Bus into the FIFO. Again, since the DS3134 can handle
multiple HDLC channels, it is quite possible that at any one time, several HDLC channels will need the
DMA to burst data from the PCI Bus into the FIFO. The FIFO determines which HDLC channel the
DMA will handle next via a Host configurable algorithm, which allows the selection to be either round
robin or priority, decoded (with HDLC Channel 1 getting the highest priority).
11 of 203
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DS3134.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DS3130 | 5-Port Pilot Solenoid Valve Body Ported Type / Base Ported Type |  TPC |
| DS3134 | Chateau Channelized T1 And E1 And HDLC Controller | Dallas Semiconducotr |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |