|
|
PDF DS2433 Data sheet ( Hoja de datos )
| Número de pieza | DS2433 | |
| Descripción | 4k-Bit 1-Wire EEPROM | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de DS2433 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
|
No Preview Available !
www.dalsemi.com
PRELIMINARY
DS2433
4k-Bit 1-WireTM EEPROM
FEATURES
§ 4096 bits Electrically Erasable Programmable
Read Only Memory (EEPROM)
§ Unique, factory-lasered and tested 64-bit
registration number (8-bit family code + 48-
bit serial number + 8-bit CRC tester) assures
absolute identity because no two parts are
alike
§ Built-in multidrop controller ensures
compatibility with other MicroLAN products
§ Memory partitioned into sixteen 256-bit pages
for packetizing data
§ 256-bit scratchpad with strict read/write
protocols ensures integrity of data transfer
§ Reduces control, address, data and power to a
single data pin
§ Directly connects to a single port pin of a
microprocessor and communicates at up to
16.3k bits per second
§ Overdrive mode boosts communication speed
to 142k bits per second
§ 8-bit family code specifies DS2433
communication requirements to reader
§ Presence detector acknowledges when reader
first applies voltage
§ Low cost PR-35 or 8-pin SOIC surface mount
package
§ Reads and writes over a wide voltage range of
2.8V to 6.0V from -40°C to +85°C
PIN ASSIGNMENT
NC 1 8 NC
NC 2 7 NC
DATA 3 6 NC
GND 4 5 NC
8-PIN SOIC (208 MIL)
123
1 2 3 PR-35
BOTTOM VIEW
PIN DESCRIPTION
PR-35
Pin 1
Ground
Pin 2
Data
Pin 3
NC
Pin 4
--
Pin 5-8
--
SOIC
NC
NC
Data
Ground
NC
ORDERING INFORMATION
DS2433
PR-35 package
DS2433S 8-pin SOIC package
DS2433T Tape & Reel version of DS2433
DS2433Y Tape & Reel version of DS2433S
DS2433X Chip Scale Pkg., Tape & Reel
SILICON LABEL DESCRIPTION
The DS2433 4K-bit 1-Wire EEPROM identifies and stores relevant information about the product to
which it is associated. This lot or product specific information can be accessed with minimal interface,
for example a single port pin of a microcontroller. The DS2433 consists of a factory-lasered registration
number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (23h) plus
4096 bits of user-programmable EEPROM. The power to read and write the DS2433 is derived entirely
1 of 19
062299
1 page  
DS2433
MEMORY FUNCTION COMMANDS
The “Memory Function Flow Chart” (Figure 7) describes the protocols necessary for accessing the
memory. An example follows the flowchart. The communication between master and DS2433 takes
place either at regular speed (default, OD = 0) or at Overdrive Speed (OD = 1). If not explicitly set into
the Overdrive Mode the DS2433 assumes regular speed.
WRITE SCRATCHPAD COMMAND [0FH]
After issuing the write scratchpad command, the master must first provide the 2-byte target address,
followed by the data to be written to the scratchpad. The data will be written to the scratchpad starting at
the byte offset (T4:T0). The ending offset (E4:E0) will be the byte offset at which the master stops
writing data. Only full data bytes are accepted. If the last data byte is incomplete its content will be
ignored and the partial byte flag PF will be set.
When executing the Write Scratchpad command the CRC generator inside the DS2433 (see Figure 12)
calculates a CRC over the entire data stream, starting at the command code and ending at the last data
byte sent by the master. This CRC is generated using the CRC16 polynomial by first clearing the CRC
generator and then shifting in the command code (0FH) of the Write Scratchpad command, the Target
Addresses TA1 and TA2 as supplied by the master and all the data bytes. The master may end the Write
Scratchpad command at any time. However, if the ending offset is 11111b, the master may send 16 read
time slots and will receive the CRC generated by the DS2433.
The memory address range of the DS2433 is 0000H to 01FFH. If the bus master sends a target address
higher than this, the internal circuitry of the chip will set the seven most significant address bits to zero as
they are shifted into the internal address register. The Read Scratchpad command will reveal the target
address as it will be used by the DS2433. The master will identify such address modifications by
comparing the target address read back to the target address transmitted. If the master does not read the
scratchpad, a subsequent copy scratchpad command will not work since the most significant bits of the
target address the master sends will not match the value the DS2433 expects.
READ SCRATCHPAD COMMAND [AAH]
This command is used to verify scratchpad data and target address. After issuing the read scratchpad
command, the master begins reading. The first two bytes will be the target address. The next byte will be
the ending offset/data status byte (E/S) followed by the scratchpad data beginning at the byte offset (T4:
T0). The master may read data until the end of the scratchpad after which the data read will be all logic
1’s.
COPY SCRATCHPAD [55H]
This command is used to copy data from the scratchpad to memory. After issuing the copy scratchpad
command, the master must provide a 3-byte authorization pattern which can be obtained by reading the
scratchpad for verification. This pattern must exactly match the data contained in the three address
registers (TA1, TA2, E/S, in that order). If the pattern matches, the AA (Authorization Accepted) flag
will be set and the copy will begin. Copy takes 5 ms maximum during which the voltage on the 1-Wire
bus must not fall below 2.8V. A pattern of alternating 1s and 0s will be received after the data has been
copied until a Reset Pulse is issued by the master.
The data to be copied is determined by the three address registers. The scratchpad data from the
beginning offset through the ending offset, will be copied to memory, starting at the target address.
Anywhere from 1 to 32 bytes may be copied to memory with this command.
5 of 19
5 Page 
DS2433
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence
consists of a Reset Pulse transmitted by the bus master followed by Presence Pulse(s) transmitted by the
slave(s).
The Presence Pulse lets the bus master know that the DS2433 is on the bus and is ready to operate. For
more details, see the “1-Wire Signaling” section.
ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of the six ROM function commands. All
ROM function commands are eight bits long. A list of these commands follows (refer to flowchart in
Figure 9):
READ ROM [33H]
This command allows the bus master to read the DS2433’s 8-bit family code, unique 48-bit serial
number, and 8-bit CRC. This command can only be used if there is a single DS2433 on the bus. If more
than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same
time (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number
will result in a mismatch of the CRC.
MATCH ROM [55H]
The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a
specific DS2433 on a multidrop bus. Only the DS2433 that exactly matches the 64-bit ROM sequence
will respond to the following memory function command. All slaves that do not match the 64-bit ROM
sequence will wait for a Reset Pulse. This command can be used with a single or multiple devices on the
bus.
SKIP ROM [CCH]
This command can save time in a single drop bus system by allowing the bus master to access the
memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus
and a read command is issued following the Skip ROM command, data collision will occur on the bus as
multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result).
SEARCH ROM [F0H]
When a system is initially brought up, the bus master might not know the number of devices on the 1-
Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process
of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process
is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the
desired value of that bit. The bus master performs this simple, 3-step routine on each bit of the ROM.
After one complete pass, the bus master knows the contents of the ROM in one device. The remaining
number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the
Book of DS19xx iButton Standards for a comprehensive discussion of a search ROM, including an actual
example.
OVERDRIVE SKIP ROM [3CH]
On a single-drop bus this command can save time by allowing the bus master to access the memory
functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command the
Overdrive Skip ROM sets the DS2433 in the Overdrive Mode (OD = 1). All communication following
11 of 19
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet DS2433.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DS2430 | 256-Bit 1-Wire EEPROM | Dallas Semiconducotr |
| DS2430A | 256-Bit 1-Wire EEPROM |  Maxim Integrated |
| DS2431 | 1024-Bit 1-Wire EEPROM | Dallas Semiconducotr |
| DS2431 | 1-Wire EEPROM | Maxim Integrated |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |