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PDF DS21Q48N Data sheet ( Hoja de datos )

Número de pieza DS21Q48N
Descripción 5V E1/T1/J1 Line Interface
Fabricantes Dallas Semiconducotr 
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FEATURES
§ Complete E1, T1, or J1 line interface unit
(LIU)
§ Supports both long- and short-haul trunks
§ Internal software-selectable receive-side
termination for 75/100/120W
§ 5V power supply
§ 32-bit or 128-bit crystal-less jitter attenuator
requires only a 2.048MHz master clock for
both E1 and T1 with option to use 1.544MHz
for T1
§ Generates the appropriate line build outs,
with and without return loss, for E1 and
DSX-1 and CSU line build outs for T1
§ AMI, HDB3, and B8ZS, encoding/decoding
§ 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz clock output synthesized to
recovered clock
§ Programmable monitor mode for receiver
§ Loopbacks and PRBS pattern generation/
detection with output for received errors
§ Generates/detects in-band loop codes, 1 to 16
bits including CSU loop codes
§ 8-bit parallel or serial interface with optional
hardware mode
§ Multiplexed and nonmultiplexed parallel bus
supports Intel or Motorola
§ Detects/generates blue (AIS) alarms
§ NRZ/bipolar interface for TX/RX data I/O
§ Transmit open-circuit detection
§ Receive Carrier Loss (RCL) indication
(G.775)
§ High-Z State for TTIP and TRING
§ 50mA (rms) current limiter
DS2148/DS21Q48
5V E1/T1/J1 Line Interface
PIN DESCRIPTION
44
1
44 TQFP
7mm
CABGA
ORDERING INFORMATION
Single-Channel Devices:
DS2148TN 44-Pin TQFP (-40°C to +85°C)
DS2148T 44-Pin TQFP (0o C to +70o C)
DS2148GN 7mm CABGA (-40°C to +85°C)
DS2148G 7mm CABGA (0o C to +70o C)
Four-Channel Devices:
DS21Q48N (Quad) BGA (-40°C to +85°C)
DS21Q48 (Quad) BGA (0o C to +70oC)
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REV: 082504

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DS21Q48N pdf
2. LIST OF TABLES
DS2148/Q48
Table 4-1 BUS INTERFACE SELECTION ................................................................................................ 9
Table 4-2a PIN ASSIGNMENT................................................................................................................. 10
Table 4-2b PIN DESCRIPTIONS (Sorted by Pin Name, DS2148T Pin Numbering) ............................... 11
Table 4-3a PIN ASSIGNMENT IN SERIAL PORT MODE..................................................................... 13
Table 4-3b PIN DESCRIPTIONS IN SERIAL PORT MODE (Sorted by Pin Name, DS2148T Pin
Numbering) .......................................................................................................................................... 14
Table 4-4a PIN ASSIGNMENT IN HARDWARE MODE....................................................................... 16
Table 4-4b PIN DESCRIPTIONS IN HARDWARE MODE (Sorted by Pin Name, DS2148T Pin
Numbering) .......................................................................................................................................... 16
Table 4-5 LOOPBACK CONTROL IN HARDWARE MODE ................................................................ 20
Table 4-6 TRANSMIT DATA CONTROL IN HARDWARE MODE ..................................................... 20
Table 4-7 RECEIVE SENSITIVITY SETTINGS...................................................................................... 20
Table 4-8 MONITOR GAIN SETTINGS .................................................................................................. 20
Table 4-9 INTERNAL RX TERMINATION SELECT............................................................................. 20
Table 4-10 MCLK SELECTION................................................................................................................ 20
Table 5-1 REGISTER MAP ....................................................................................................................... 23
Table 6-1 MCLK SELECTION.................................................................................................................. 29
Table 6-2 RECEIVE SENSITIVITY SETTINGS...................................................................................... 31
Table 6-3 BACK PLANE CLOCK SELECT............................................................................................. 32
Table 6-4 MONITOR GAIN SETTINGS .................................................................................................. 32
Table 6-5 INTERNAL RX TERMINATION SELECT............................................................................. 33
Table 7-1 RECEIVED ALARM CRITERIA ............................................................................................. 35
Table 7-2 RECEIVE LEVEL INDICATION............................................................................................. 38
Table 8-1 TRANSMIT CODE LENGTH................................................................................................... 40
Table 8-2 RECEIVE CODE LENGTH ...................................................................................................... 40
Table 8-3 DEFINITION OF RECEIVED ERRORS.................................................................................. 44
Table 8-4 FUNCTION OF ECRS BITS AND RNEG PIN ........................................................................ 45
Table 9-1 LINE BUILD OUT SELECT FOR E1 IN REGISTER CCR4 (ETS = 0) ................................. 48
Table 9-2 LINE BUILD OUT SELECT FOR T1 IN REGISTER CCR4 (ETS = 1) ................................. 48
Table 9-3 TRANSFORMER SPECIFICATIONS FOR 5V OPERATION ............................................... 49
Table 10-1 DS21Q48 PIN ASSIGNMENT................................................................................................ 56
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DS21Q48N arduino
DS2148/Q48
PIN DESCRIPTIONS IN PARALLEL PORT MODE (Sorted by Pin Name,
DS2148T Pin Numbering) Table 4-2b
ACRONYM PIN
I/O DESCRIPTION
A0 11 I Address Bus. In nonmultiplexed bus operation (BIS1 = 0, BIS0 =
To to
1), serves as the address bus. In multiplexed bus operation (BIS1 =
A4 7
0, BIS0 = 0), these pins are not used and should be tied low.
ALE
4 I Address Latch Enable (Address Strobe). When using the parallel
(AS)
port (BIS1 = 0) in multiplexed bus mode (BIS0 = 0), serves to
demultiplex the bus on a positive-going edge. In nonmultiplexed bus
mode (BIS0 = 1), should be tied low.
BIS0/ 32/ I Bus Interface Select Bits 0 & 1. Used to select bus interface option.
BIS1
33
See Table 4-1 for details.
BPCLK 31 O Back Plane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz clock output that is referenced to RCLK selectable via
CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384MHz
output.
CS* 1 I Chip Select. Must be low to read or write to the device. CS* is an
active low signal.
D0 / AD0
19
I/O Data Bus/Address/Data Bus. In non-multiplexed bus operation
To to
(BIS1 = 0, BIS0 = 1), serves as the data bus. In multiplexed bus
D7 / AD7
12
operation (BIS1 = 0, BIS0 = 0), serves as an 8-bit multiplexed
address/data bus.
HRST*
29
I Hardware Reset. Bringing HRST* low will reset the DS2148
setting all control bits to their default state of all zeros.
INT*
23 O Interrupt [INT*] pin 23. Flags host controller during conditions
and change of conditions defined in the Status Register. Active low,
open drain output.
MCLK
30
I Master Clock. A 2.048MHz (±50ppm) clock source with TTL
levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz
clock source is optional.
See Note 1 on clock accuracy at the end of this table.
NA - I Not Assigned. Should be tied low.
PBEO
24 O PRBS Bit Error Output. The receiver will constantly search for a
215-1 or a 220-1 PRBS depending on the ETS bit setting (CCR1.7).
Remains high if out of synchronization with the PRBS pattern. Goes
low when synchronized to the PRBS pattern. Any errors in the
received pattern after synchronization will cause a positive going
pulse (with same period as E1 or T1 clock) synchronous with
RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2
registers by setting CCR6.2 to a logic 1.
PBTS 44 I Parallel Bus Type Select. When using the parallel port (BIS1 = 0),
set high to select Motorola bus timing, set low to select Intel bus
timing. This pin controls the function of the RD*(DS*), ALE(AS),
and WR*(R/W*) pins. If PBTS = 1 and BIS1 = 0, then these pins
assume the Motorola function listed in parenthesis (). In serial port
mode, this pin should be tied low.
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