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PDF DS21Q44 Data sheet ( Hoja de datos )

Número de pieza DS21Q44
Descripción Enhanced QUAD E1 FRAMER
Fabricantes Dallas Semiconducotr 
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No Preview Available ! DS21Q44 Hoja de datos, Descripción, Manual

DS21Q44
Enhanced QUAD E1 FRAMER
www.dalsemi.com
FEATURES
Four E1 (CEPT or PCM-30) /ISDN-PRI
framing transceivers
All four framers are fully independent;
transmit and receive sections of each framer
are fully independent
Frames to FAS, CAS, CCS, and CRC4 formats
Each of the four framers contain dual two–
frame elastic store slip buffers that can
connect to asynchronous backplanes up to
8.192 MHz
8–bit parallel control port that can be used
directly on either multiplexed or non–
multiplexed buses (Intel or Motorola)
Easy access to Si and Sa bits
Extracts and inserts CAS signaling
Large counters for bipolar and code
violations, CRC4 code word errors, FAS
word errors, and E-bits
Programmable output clocks for Fractional
E1, per channel loopback, H0 and H12
applications
Integral HDLC controller with 64-byte buffers
configurable for Sa bits or DS0 operation
Detects and generates AIS, remote alarm,
and remote multiframe alarms
Pin compatible with DS21Q42 Enhanced
Quad T1 Framer
3.3V supply with 5V tolerant I/O; low power
CMOS
Available in 128–pin TQFP package
IEEE 1149.1 support
FUNCTIONAL DIAGRAM
Receive
Framer
Elastic
Store
Transmit
Formatter
FRAMER #0
FRAMER #1
FRAMER #2
FRAMER #3
Elastic
Store
Control Port
ACTUAL SIZE
QUAD
E1
FRAMER
ORDERING INFORMATION
DS21Q44T (00 C to 700 C)
DS21Q44TN (-400 C to +850 C)
DESCRIPTION
The DS21Q44 E1 is an enhanced version of the DS21Q43 Quad E1 Framer. The DS21Q44 contains four
framers that are configured and read through a common microprocessor compatible parallel port. Each
framer consists of a receive framer, receive elastic store, transmit formatter and transmit elastic store. All
four framers in the DS21Q44 are totally independent, they do not share a common framing synchronizer.
Also the transmit and receive sides of each framer are totally independent. The dual two-frame elastic
stores contained in each of the four framers can be independently enabled and disabled as required. The
device fully meets all of the latest E1 specifications including CCITT/ITU G.704, G.706, G.962, and
I.431 as well as ETS 300 011 and ETS 300 233.
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DS21Q44 pdf
DS21Q44
15. HDLC CONTROLLER FOR THE SA BITS OR DS0 ................................................................. 59
15.1 GENERAL OVERVIEW........................................................................................................... 59
15.2 HDLC STATUS REGISTERS .................................................................................................. 60
15.3 BASIC OPERATION DETAILS............................................................................................... 61
15.4 HDLC REGISTER DESCRIPTION.......................................................................................... 62
16. INTERLEAVED PCM BUS OPERATION ................................................................................... 69
17. JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT .......................... 72
17.1 DESCRIPTION.......................................................................................................................... 72
17.2 TAP CONTROLLER STATE MACHINE................................................................................ 73
17.3 INSTRUCTION REGISTER AND INSTRUCTIONS ............................................................. 75
17.4 TEST REGISTERS.................................................................................................................... 77
18. TIMING DIAGRAMS...................................................................................................................... 82
19. OPERATING PARAMETERS ...................................................................................................... 92
20. 128-PIN TQFP PACKAGE SPECIFICATIONS ........................................................................ 105
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DS21Q44 arduino
PIN
SYMBOL
TYPE
DESCRIPTION
84 JTDI
86 JTDO
50 JTMS
18 JTRST*
64 MUX
10 RCHBLK0
44 RCHBLK1
80 RCHBLK2
104 RCHBLK3
6 RCLK0
40 RCLK1
74 RCLK2
100 RCLK3
62 RD*/(DS*)
17 RFSYNC0
51 RFSYNC1
85 RFSYNC2
109 RFSYNC3
5 RLCLK0
39 RLCLK1
73 RLCLK2
99 RLCLK3
4 RLINK0
38 RLINK1
72 RLINK2
98 RLINK3
7 RNEG0
41 RNEG1
75 RNEG2
101 RNEG3
8 RPOS0
42 RPOS1
76 RPOS2
102 RPOS3
13 RSER0
49 RSER1
83 RSER2
107 RSER3
9 RSIG0
43 RSIG1
77 RSIG2
103 RSIG3
12 RSYNC0
48 RSYNC1
82 RSYNC2
I JTAG Test Data Input
O JTAG Test Data Output
I JTAG Test Mode Select
I JTAG Reset
I Non-Multiplexed or Multiplexed Bus Select
O Receive Channel Block from Framer 0
O Receive Channel Block from Framer 1
O Receive Channel Block from Framer 2
O Receive Channel Block from Framer 3
I Receive Clock for Framer 0
I Receive Clock for Framer 1
I Receive Clock for Framer 2
I Receive Clock for Framer 3
I Read Input (Data Strobe)
O Receive Frame Sync from Framer 0
O Receive Frame Sync from Framer 1
O Receive Frame Sync from Framer 2
O Receive Frame Sync from Framer 3
O Receive Link Clock from Framer 0
O Receive Link Clock from Framer 1
O Receive Link Clock from Framer 2
O Receive Link Clock from Framer 3
O Receive Link Data from Framer 0
O Receive Link Data from Framer 1
O Receive Link Data from Framer 2
O Receive Link Data from Framer 3
I Receive Bipolar Data for Framer 0
I Receive Bipolar Data for Framer 1
I Receive Bipolar Data for Framer 2
I Receive Bipolar Data for Framer 3
I Receive Bipolar Data for Framer 0
I Receive Bipolar Data for Framer 1
I Receive Bipolar Data for Framer 2
I Receive Bipolar Data for Framer 3
O Receive Serial Data from Framer 0
O Receive Serial Data from Framer 1
O Receive Serial Data from Framer 2
O Receive Serial Data from Framer 3
O Receive Signaling Output from Framer 0
O Receive Signaling output from Framer 1
O Receive Signaling Output from Framer 2
O Receive Signaling Output from Framer 3
I/O Receive Sync for Framer 0
I/O Receive Sync for Framer 1
I/O Receive Sync for Framer 2
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DS21Q44

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