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PDF DS21Q43ATN Data sheet ( Hoja de datos )

Número de pieza DS21Q43ATN
Descripción Quad E1 Framer
Fabricantes Dallas Semiconducotr 
Logotipo Dallas Semiconducotr Logotipo



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No Preview Available ! DS21Q43ATN Hoja de datos, Descripción, Manual

DS21Q43A
Quad E1 Framer
www.dalsemi.com
FEATURES
§ Four E1 (CEPT or PCM-30) /ISDN-PRI
framing transceivers
§ All four framers are fully independent;
transmit and receive sections of each framer
are fully independent
§ Frames to FAS, CAS, CCS, and CRC4
formats
§ 8-bit parallel control port that can be
connected to either multiplexed or non-
multiplexed buses
§ Each of the four framers contains dual two-
frame elastic stores that can connect to
asynchronous or synchronous backplanes up
to 8.192 MHz
§ Easy access to Si and Sa bits
§ Extracts and inserts CAS signaling
§ Large counters for bipolar and code
violations, CRC4 code word errors, FAS
word errors, and E-bits
§ Programmable output clocks for Fractional
E1, per channel loopback, H0 and H12
applications
§ Detects and generates AIS, remote alarm, and
remote multiframe alarms
§ Pin-compatible with DS21Q41B Quad T1
Framer
§ 5V supply; low power CMOS
§ Available in 128-pin TQFP
§ Industrial (-40°C to +85°C) grade version
available (DS21Q43ATN)
FUNCTIONAL DIAGRAM
RECEIVE
FRAMER
TRANSMIT
FORMATTER
ELASTIC
STORE
ELASTIC
STORE
FRAMER #0
FRAMER #1
FRAMER #2
FRAMER #3
CONTROL PORT
ACTUAL SIZE
QUAD
E1
FRAMER
DESCRIPTION
The DS21Q43A combines four of the popular DS2143 E1 Controllers onto a single monolithic die. The
“A” designation denotes that some new features are available in the Quad version which were not
available in the single E1 device. The added features in the DS21Q43A are listed in Section 1. The
DS21Q43A offers a substantial space savings to applications that require more than one E1 framer on a
card. The Quad version is only slightly bigger than the single E1 device. All four framers in the
DS21Q43A are totally independent; they do not share a common framing synchronizer. Also, the transmit
and receive sides of each framer are totally independent. The dual two-frame elastic stores contained in
each of the four framers can be independently enabled and disabled as required. The DS21Q43A meets
all of the latest specifications, including CCITT/ITU G.704, G.706, G.962, and I.431 as well as ETS 300
011 and ETS 300 233.
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DS21Q43ATN pdf
TRANSMIT PIN LIST Table 1-1
PIN SYMBOL TYPE
DESCRIPTION
19 TCLK0
I Transmit Clock for Framer 0
53 TCLK1
I Transmit Clock for Framer 1
87 TCLK2
I Transmit Clock for Framer 2
113 TCLK3
I Transmit Clock for Framer 3
126 TSER0
I Transmit Serial Data for Framer 0
32 TSER1
I Transmit Serial Data for Framer 1
66 TSER2
I Transmit Serial Data for Framer 2
92 TSER3
I Transmit Serial Data for Framer 3
128 TCHCLK0
O Transmit Channel Clock from Framer 0
34 TCHCLK1
O Transmit Channel Clock from Framer 1
68 TCHCLK2
O Transmit Channel Clock from Framer 2
94 TCHCLK3
O Transmit Channel Clock from Framer 3
1 TCHBLK0
O Transmit Channel Block from Framer 0
35 TCHBLK1
O Transmit Channel Block from Framer 1
69 TCHBLK2
O Transmit Channel Block from Framer 2
95 TCHBLK3
O Transmit Channel Block from Framer 3
20 TLCLK0
O Transmit Link Clock from Framer 0
54 TLCLK1
O Transmit Link Clock from Framer 1
88 TLCLK2
O Transmit Link Clock from Framer 2
114 TLCLK3
O Transmit Link Clock from Framer 3
22 TLINK0
I Transmit Link Data for Framer 0
56 TLINK1
I Transmit Link Data for Framer 1
90 TLINK2
I Transmit Link Data for Framer 2
116 TLINK3
I Transmit Link Data for Framer 3
2 TPOS0
O Transmit Bipolar Data from Framer 0
36 TPOS1
O Transmit Bipolar Data from Framer 1
70 TPOS2
O Transmit Bipolar Data from Framer 2
96 TPOS3
O Transmit Bipolar Data from Framer 3
3 TNEG0
O Transmit Bipolar Data from Framer 0
37 TNEG1
O Transmit Bipolar Data from Framer 1
71 TNEG2
O Transmit Bipolar Data from Framer 2
97 TNEG3
O Transmit Bipolar Data from Framer 3
21 TSYNC0
I/O Transmit Sync for Framer 0
55 TSYNC1
I/O Transmit Sync for Framer 1
89 TSYNC2
I/O Transmit Sync for Framer 2
115 TSYNC3
I/O Transmit Sync for Framer 3
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DS21Q43ATN arduino
DS21Q43A
Data Bus [D0 to D7] or Address/Data Bus [AD0 to AD7]. In non-multiplexed bus operation (MUX=0),
serves as the data bus. In multiplexed bus operation (MUX=1), serves as an 8-bit multiplexed
address/data bus.
Address Bus [A0 to A5]. In non-multiplexed bus operation (MUX=0), serves as the address bus. In
multiplexed bus operation (MUX=1), these pins are not used and should be tied low.
Bus Type Select [BTS]. Strap high to select Motorola bus timing; strap low to select Intel bus timing.
This pin controls the function of the RD (DS), ALE(AS), and WR (R/ W ) pins. If BTS=1, then these pins
assume the function listed in parentheses ().
Read Input [ RD ] (Data Strobe [DS]).
Framer Selects [FS0 and FS1]. Selects which of the four framers to be accessed.
Chip Selects [ CS ]. Must be low to read or write to any of the four framers.
A6 or Address Latch Enable [ALE] (Address Strobe [AS]). In non-multiplexed bus operation
(MUX=0), serves as the upper address bit. In multiplexed bus operation (MUX=1), serves to demultiplex
the bus on a positive-going edge.
Write Input [ WR ] (Read/Write [R/ W ]).
Positive Supply [VDD]. 5.0 volts ± 0.5 volts.
Signal Ground [VSS]. 0.0 volts.
DS21Q43A FRAMER DECODE Table 1-5
FS1 FS0
00
01
10
11
FRAMER ACCESSED
#0
#1
#2
#3
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