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PDF DS21Q41B Data sheet ( Hoja de datos )
| Número de pieza | DS21Q41B | |
| Descripción | Quad T1 Framer | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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DS21Q41B
Quad T1 Framer
FEATURES
§ Four T1 DS1/ISDN-PRI framing transceivers
§ All four framers are fully independent
§ Frames to D4, ESF, and SLC-96 formats
§ 8-bit parallel control port that can be
connected to either multiplexed or non-
multiplexed buses
§ Each of the four framers contains dual two-
frame elastic stores that can connect to
asynchronous or synchronous backplanes up
to 8.192 MHz
§ Extracts and inserts robbed bit signaling
§ Framer and payload loopbacks
§ Large counters for BPVs, LCVs, EXZs,
CRC6, PCVs, F-bit errors and the number of
multiframes out of sync
§ Contains ANSI 1s density monitor and
enforcer
§ CSU loop code generator and detector
§ Programmable output clocks for Fractional
T1, ISDN-PRI, Actual Size and per channel
loopback applications
§ Onboard FDL support circuitry
§ Pin-compatible with DS21Q43 Quad E1
Framer
§ 5V supply; low power CMOS
§ Available in 128-pin TQFP
§ Industrial (-40°C to +85°C) grade version
available (DS21Q41BTN)
FUNCTIONAL DIAGRAM
RECEIVE
FRAMER
ELASTIC
STORE
TRANSMIT
FORMATTER
ELASTIC
STORE
FRAMER #0
FRAMER #1
FRAMER #2
FRAMER #3
CONTROL PORT
ACTUAL SIZE
QUAD
T1
FRAMER
DESCRIPTION
The DS21Q41B combines four of the popular DS2141A T1 Controllers onto a single monolithic die. The
“B” designation denotes that some new features are available in the Quad version that were not available
in the single T1 device. The added features in the DS21Q41B are listed in Section 1. The DS21Q41B
offers a substantial space savings to applications that require more than one T1 framer on a card. The
Quad version is only slightly bigger than the single T1 device. All four framers in the DS21Q41B are
totally independent; they do not share a common framing synchronizer. Also, the transmit and receive
sides of each framer are totally independent. The dual two-frame elastic stores contained in each of the
four framers can be independently enabled and disabled as required. The DS21Q41B meets all of the
latest specifications including ANSI T1.403 (and the emerging T1.403-199X), ANSI T1.231-1993,
AT&T TR62411, AT&T TR54016, ITU G.704 and G.706.
1 of 61
092299
1 page  
127 TFSYNC0
33 TFSYNC1
67 TFSYNC2
93 TFSYNC3
125 TSYSCLK0
31 TSYSCLK1
65 TSYSCLK2
91 TSYSCLK3
DS21Q41B
I Transmit Sync for Elastic Store in Framer 0
I Transmit Sync for Elastic Store in Framer 1
I Transmit Sync for Elastic Store in Framer 2
I Transmit Sync for Elastic Store in Framer 3
I Transmit System Clock for Elastic Store in Framer 0
I Transmit System Clock for Elastic Store in Framer 1
I Transmit System Clock for Elastic Store in Framer 2
I Transmit System Clock for Elastic Store in Framer 3
RECEIVE PIN LIST Table 1-2
PIN SYMBOL TYPE
DESCRIPTION
6 RCLK0
I Receive Clock for Framer 0
40 RCLK1
I Receive Clock for Framer 1
74 RCLK2
I Receive Clock for Framer 2
100 RCLK3
I Receive Clock for Framer 3
13 RSER0
O Receive Serial Data from Framer 0
49 RSER1
O Receive Serial Data from Framer 1
83 RSER2
O Receive Serial Data from Framer 2
107 RSER3
O Receive Serial Data from Framer 3
9 RCHCLK0
O Receive Channel Clock from Framer 0
43 RCHCLK1
O Receive Channel Clock from Framer 1
77 RCHCLK2
O Receive Channel Clock from Framer 2
103 RCHCLK3
O Receive Channel Clock from Framer 3
10 RCHBLK0
O Receive Channel Block from Framer 0
44 RCHBLK1
O Receive Channel Block from Framer 1
80 RCHBLK2
O Receive Channel Block from Framer 2
104 RCHBLK3
O Receive Channel Block from Framer 3
5 RLCLK0
O Receive Link Clock from Framer 0
39 RLCLK1
O Receive Link Clock from Framer 1
73 RLCLK2
O Receive Link Clock from Framer 2
99 RLCLK3
O Receive Link Clock from Framer 3
4 RLINK0
O Receive Link Data from Framer 0
38 RLINK1
O Receive Link Data from Framer 1
72 RLINK2
O Receive Link Data from Framer 2
98 RLINK3
O Receive Link Data from Framer 3
8 RPOS0
I Receive Bipolar Data for Framer 0
42 RPOS1
I Receive Bipolar Data for Framer 1
76 RPOS2
I Receive Bipolar Data for Framer 2
5 of 61
5 Page 
DS21Q41B REGISTER MAP Table 1-5
ADDRESS R/W
REGISTER NAME
20 R/W Status Register 1
21 R/W Status Register 2
22 R/W Receive Information Register 1
23 R Line Code Violation Count Register 1
24 R Line Code Violation Count Register 2
25 R Path Code Violation Count Register 1(1)
26 R Path Code Violation Count Register 2
27 R Multiframe Out of Sync Count Register 2
28 R Receive FDL Register
29 R/W Receive FDL Match Register 1
2A R/W Receive FDL Match Register 2
2B R/W Receive Control Register 1
2C R/W Receive Control Register 2
2D R/W Receive Mark Register 1
2E R/W Receive Mark Register 2
2F R/W Receive Mark Register 3
30 R/W Common Control Register 3
31 R/W Receive Information Register 2
32 R/W Transmit Channel Blocking Register 1
33 R/W Transmit Channel Blocking Register 2
34 R/W Transmit Channel Blocking Register 3
35 R/W Transmit Control Register 1
36 R/W Transmit Control Register 2
37 R/W Common Control Register 1
38 R/W Common Control Register 2
39 R/W Transmit Transparency Register 1
3A R/W Transmit Transparency Register 2
3B R/W Transmit Transparency Register 3
3C R/W Transmit Idle Register 1
3D R/W Transmit Idle Register 2
3E R/W Transmit Idle Register 3
3F R/W Transmit Idle Definition Register
60 R Receive Signaling Register 1
61 R Receive Signaling Register 2
62 R Receive Signaling Register 3
63 R Receive Signaling Register 4
11 of 61
DS21Q41B
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DS21Q41B.PDF ] | |
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