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PDF DS21Q354 Data sheet ( Hoja de datos )

Número de pieza DS21Q354
Descripción Quad T1/E1 Transceiver 5V
Fabricantes Dallas Semiconducotr 
Logotipo Dallas Semiconducotr Logotipo



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No Preview Available ! DS21Q354 Hoja de datos, Descripción, Manual

DALLAS SEMICONDUCTOR
Quad T1/E1 Transceiver (5V)
Quad T1/E1 Transceiver (3.3V)
Preliminary
DS21Q552/DS21Q554
DS21Q352/DS21Q354
FEATURES
P
Four (4) Completely Independent T1 or E1 Transceivers
In One Small 27mm x 27mm Package
Each Transceiver Contains a Short & Long Haul Line Interface
Plus a Full Featured Framer with Alarm Detection/Generation,
Elastic Stores, Hardware Based Signaling Support, Per DS0
Channel Control and HDLC Controller
Each Multi-Chip Module (MCM) Contains Four Die of:
DS21352 (DS21Q352)
DS21552 (DS21Q552)
DS21354 (DS21Q354)
DS21554 (DS21Q554)
Selection Guide:
Supply
Device
T1 3.3V
T1 5V
E1 3.3V
E1 5V
DS21Q352
DS21Q552
DS21Q354
DS21Q554
See the Specific DS21352/DS21552 and DS21354/DS21554
Data Sheets for Details on their Feature Set and Operation
All Four T1 or E1 Transceivers Can be Concatenated into a Single
8.192MHz Backplane Data Stream
IEEE 1149.1 JTAG-Boundary Scan Architecture
DS21Q352/DS21Q552 and DS21Q354/DS21Q554 are Pin Compatible
to Allow the Same Footprint to Support T1 and E1 Applications
256–lead MCM BGA package (27mm X 27mm)
Low Power 5V CMOS or Low Power 3.3V CMOS with 5V
Tolerant Input & Outputs
DESCRIPTION
The Quad T1 and E1 Transceiver MCMs offer a high density packaging arrangement for the
DS21352/DS21552 T1 Single-Chip Transceivers and the DS21354/DS21554 E1 Single-Chip Transceivers.
Four silicon die of one of these devices is packaged in a Multi-Chip Module (MCM) with the electrical
connections as shown in Figure 1. All of the functions available on the DS21352/DS21552 and
DS21354/DS21554 are also available in the MCM packaged version however in order to minimize package
size, some signals have been deleted. These differences are detailed in Table 1.
This data sheet describes the electrical connections and the mechanical dimensions only. Please see the
DS21352/DS21552 and DS21354/DS21554 data sheets for full details on all of the features and the
operating characteristics of the device.
December 29, 1998

1 page




DS21Q354 pdf
DALLAS SEMICONDUCTOR DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
DS21Q352 / DS21Q552 / DS21Q354 / DS21Q554 Schematic Figure 1 (continued)
See Connecting Page
RCLKO
RPOSO
SCT # 4
RNEGO
RCLKI
RPOSI
RNEGI
TCLKO
DS21352 / DS21552 /
DS21354 / DS21554
Signals Not Connected & Left Open Circuited
Include: 8XCLK / XTALD / RDATA / RCL
CO
CI
TPOSO
RCLK
TNEGO
RLOS/LOTC
TCLKI
8MCLK
TPOSI
RLINK
TNEGI
RLCLK
LIUC
RCHBLK
TEST
BTS
MUX
WR*
RD*
A0 to A7/ALE
D0/AD0 to D7/AD7
CS*
INT*
JTRST
JTMS
JTCLK
JTDI
JTDO
MCLK
RCHCLK
RSIGF
RSIG
RSER
RSYSCLK
RSYNC
RMSYMC
RFSYNC
TESO
TDATA
TSYNC
TSSYNC
TSYSCLK
TSER
TSIG
TCLK
RTIP
RRING
TTIP
TRING
TCHBLK
TCHCLK
TLINK
TLCLK
FMS
DVSS
RVSS
TVSS
DVDD
RVDD
TVDD
December 29, 1998
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DS21Q354 arduino
DALLAS SEMICONDUCTOR DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
DS21Q352 / DS21Q552 / DS21Q354 / DS21Q554 PCB Land Pattern Figure 2
The diagram shown below is the lead pattern that will be placed on the target PCB. This is the same
pattern that would be seen as viewed through the MCM from the top.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A rneg rf rlink rclk dvss co tclko tpos dvdd tsig tsys rlclk rlink cs rclki rpos dvss tch tsys dvss
i sync 3 i 3 3 3 i 3 3 clk 3 2 2* 2 o 2 clk clk 2
33
3
33
2 22
B rpos rposi dvdd
o33
rclk
o
33
cs dvdd dvss tch dvss tclk dvss dvdd rclk rpos rneg rsig
3* 3 3 clk 3 3 2 2 2 i o 2
3 22
co ts tclk tneg
2 sync 2
o
22
C rsig rneg dvss dvdd tvss tlink tsync tclk
tpos
tser
tch
dvdd dvss
rclk
rsigf dvdd tser
tsig
tpos tpos
3 o 3 3 3 3 3 i o 3 blk 2 2 o 2 2 2 2 o i
3
33
3
2
22
D rsync rsigf rlclk rvss rvss tlclk ci tneg tneg ts tvdd rsync rneg rch rser rm
rf dvdd tclk tsync
3 3 3 3 3 3 3 i o sync 3 2 i clk 2 sync sync 2 i 2
333
22
22
2
E rlos rser rclk rvdd
3333
rlos tclk tlink tlclk
2o22
2
F rlclk rm
1 sync
rch
clk
8m
clk
333
rsys ci tneg tch
clk 2
i blk
2 22
G rsync rlink rsys rch
1 1 clk blk
33
rch tvss tvdd dvdd
blk 2 2 4
2
H rsys rlos dvss A5
clk 1
1
1
8m jtdo rvss dvss
clk 2 2 4
2
J rch rser dvdd dvss
clk 1 1 1
1
rvdd rvss D1/
2 2 AD1
co
4
K rsigf liuc
1
wr* rf
sync
1
cs rlclk ts tser
4* 4 sync 4
4
L rm rsig rneg rpos
sync 1 o o
1 11
A1 tch tsig dvss
clk 4
4
4
M 8m rch rclk rclk
clk blk
o
i
1111
dvdd rclk
44
tclk dvdd
44
N jtdi rd* rclk dvdd
11
dvss tsys tpos tneg
4 clk o
o
444
P rvdd bts
1
cs A7/
1* ALE
rneg dvdd tclk
i 4o
44
tclk
i
4
R tneg rvss rneg rpos
i1i i
1 11
rclk tsync tpos tneg
i4i i
4 44
T mclk rvss tneg
11o
A3
1
rclk tlclk tlink
o44
4
ci
4
U int* dvdd
A0
D7/
D5/ dvss D3/
A6
D4/ mux D0/ rlink dvss rch rpos test rneg tvss tvdd tch
1
AD7 AD5 1 AD3
AD4
AD0 4
4 clk o
o 4 4 blk
44
4
4
V tsync
A2
tlclk
D6/ dvdd tclk tpos
A4
co
tch rlos rsync 8m
rf rpos rsigf jtdo3 jtrst* jtdo4 rvss
1
1 AD6 1 i o
1 clk 4
4
clk sync
i
4
4
11 1 444
W tch tvdd tpos tvss tlink ci tclk dvss tser tsig tsys ts jtms rsys D2/ rm rser rvdd rvss mclk
blk 1 i 1 1 1 o 1 1 1 clk sync
clk AD2 sync 4 4 4 2
1 1 1 11 4 4
Y ttip tring ttip tring ttip tring ttip tring tclk rtip rring rch rtip rring jtclk rtip rring rsig rtip rring
1 1 2 2 3 3 4 4 1 1 1 blk 2 2
33444
4
December 29, 1998
11

11 Page







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