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PDF DS2182A Data sheet ( Hoja de datos )
| Número de pieza | DS2182A | |
| Descripción | T1 Line Monitor | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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FEATURES
§ Performs framing and monitoring functions
Supports Superframe and Extended Super-
frame formats
§ Four onboard error counters
– 16-bit bipolar violation
– 8-bit CRC
– 8-bit OOF
– 8-bit frame bit error
§ Indication of the following
– yellow and blue alarms
– incoming B8ZS code words
– 8 and 16 zero strings
– change of frame alignment
– loss of sync
– carrier loss
§ Simple serial interface used for config-
uration, control and status monitoring
§ Burst mode allows quick access to counters
for status updates
§ Automatic counter reset feature
§ Single 5V supply; low-power CMOS tech-
nology
§ Available in 28-pin DIP and 28-pin PLCC
§ The DS2182A is upward-compatible from
the original DS2182
DS2182A
T1 Line Monitor
The updated DS2182A includes the following
changes from the original DS2182:
§ Ability to count excessive zeros
§ Severely Errored Framing Event indication
§ Updated AIS detection
§ Updated RCL detection
§ AIS and RCL alarm clear indications
PIN ASSIGNMENT
INT
SDI
SDO
CS
SCLK
NC
RYEL
RLINK
RLCLK
RCLK
RCHCLK
RSER
NC
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VDD
27 RLOS
26 RFER
25 RBV
24 RCL
23 RNEG
22 RPOS
21 RST
20 TEST
19 RSIGSEL
18 RSIGFR
17 RABCD
16 RMSYNC
15 RFSYNC
28-Pin DIP (600-mil)
DESCRIPTION
The DS2182A T1 Line Monitor Chip is a monolithic CMOS device designed to monitor real-time
performance on T1 lines. The DS2182A frames to the data on the line, counts errors, and supplies
detailed information about the status and condition of the line. Large on-board counters allow the
accumulation of errors for extended periods, which permits a single CPU to monitor a number of T1
lines. Output clocks that are synchronized to the incoming data stream are provided for easy extraction of
S-Bits, FDL bits, signaling bits, and channel data. The DS2182A meets the requirements of ANSI
T1.231.
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1 page  
DS2182A
register read or write. The following 4 bits identify the register address. The next 2 bits are reserved and
must be set to 0 for proper operation. The last bit of the address/ command word enables burst mode
when set; the burst mode causes all registers to be consecutively read or written to. Data is read and
written to the DS2182A LSB first.
CHIP SELECT AND CLOCK CONTROL
All data transfers are initiated by driving the CS input low. Input data is latched on the rising edge of
SCLK and must be valid during the previous low period of SCLK to prevent momentary corruption of
register data during writes. Data is output on the falling edge of SCLK and held to the next falling edge.
All data transfers are terminated if the CS input transitions high. Port control logic is disabled and SDO is
tri-stated when CS is high.
DATA I/O
Following the eight SCLK cycles that input an address/command byte to write, a data byte is strobed into
the addressed register on the rising edge of the next eight SCLK cycles. Following an address/command
word to read, contents of the selected register are output on the falling edges of the next eight SCLK
cycles. The SDO pin is tri-stated during device write and can be tied to SDI in applications where the host
processor has a bi-directional I/O pin.
BURST MODE
The burst mode allows all onboard registers to be consecutively written to or read by the host processor.
A burst read is used to poll all registers; RSR1 and RSR2 contents will be unaffected. This feature
minimizes device initialization time on system power-up or reset. Burst mode is initiated when ACB.7 is
set and the address is 0000. A burst is terminated by a low-high transition on CS .
ACB: ADDRESS COMMAND BYTE Figure 2
MSB
BM
-
-
ADD3
ADD2
ADD1
ADD0
LSB
R/ W
SYMBOL
BM
-
POSITION
ACB.7
ACB.6
NAME AND DESCRIPTION
Burst Mode. If set (and register address is 0000) burst read or
write is enabled.
Reserved, must be 0 for operation.
-
ADD3
ADD0
R/W
ACB.5
ACB.4
ACB.1
ACB.0
Reserved, must be 0 for operation.
MSB of register address.
LSB of register address.
Read/Write Select.
0 = write addressed register
1 = read addressed register
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5 Page 
RSR2: RECEIVE STATUS REGISTER 2 Figure 10
DS2182A
MSB
SEFE
RCLC RBLC
FERR
FECS
OOFS
CRCCS
LSB
BPVCS
SYMBOL
SEFE
RCLC
RBLC
FERR
FECS
OOFCS
CRCCS
BPVCS
POSITION
RSR2.7
RSR2.6
RSR2.5
RSR2.4
RSR2.3
RSR2.2
RSR2.1
RSR2.0
NAME AND DESCRIPTION
Severely Errored Framing Event. Set when 2 out of 6 framing
bits (Ft or FPS) are received in error.
Receive Carrier Loss Clear. Set when the carrier signal is
restored; will remain set until read.
Receive Blue Alarm Clear. Set when the Blue Alarm (AIS) is no
longer detected; will remain set until read.
Frame Bit Error. Set when FT (193S) or FPS (193E) bit errors
occur.
Frame Error Count Saturation. Set on the next frame error event
after the 8-bit Frame Error Count Register (FECR) saturates at 255.
Out Of Frame Count Saturation. Set on the next OOF event
after the 8-bit OOF Count Register (OOFCR) saturates at 255.
CRC Count Saturation. Set on the next CRC error event after the
8-bit CRC Count Register (CRCCR) saturates at 255.
Bipolar Violation Count Saturation. Set on the next BPV error
event after the 16-bit Bipolar Violation Count Register (BVCR)
saturates at 65,535.
RIMR2: RECEIVE INTERRUPT MASK REGISTER 2 Figure 11
MSB
SEFE
RCLC RBLC
FERR
FECS
OOFS CRCCS
SYMBOL
SEFE
RCLC
RBLC
POSITION
RIMR2.7
RIMR2.6
RIMR2.5
NAME AND DESCRIPTION
Severely Errored Framing Event Mask.
0 = interrupt masked
1 = interrupt enabled
Receive Carrier Loss Clear Mask.
0 = interrupt masked
1 = interrupt enabled
Receive Blue Alarm Clear Mask.
0 = interrupt masked
1 = interrupt enabled
LSB
BPVCS
11 of 25
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| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet DS2182A.PDF ] | |
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