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PDF DS2175N Data sheet ( Hoja de datos )
| Número de pieza | DS2175N | |
| Descripción | T1/CEPT Elastic Store | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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FEATURES
• Rate buffer for T1 and CEPT transmission
systems
• Synchronizes loop–timed and system timed
data streams on frame boundaries
• Ideal for T1 (1.544 MHz) to CEPT (2.048
MHz), CEPT to T1 interfaces
• Supports parallel and serial backplanes
• Buffer depth is 2 frames
• Comprehensive on–chip “slip” control logic
– Slips occur only on frame boundaries
– Outputs report slip occurrences and
direction
– Align feature allows buffer to be recentered
at any time
– Buffer depth easily monitored
• Compatible with DS2180A T1 and DS2181A
CEPT Transceivers
• Industrial temperature range of –40°C to
+85°C available, designated DS2175N
DS2175
T1/CEPT Elastic Store
PIN ASSIGNMENT
RCLKSEL
RCLK
RSER
RMSYNC
FSD
SLIP
ALN
VSS
1
2
3
4
5
6
7
8
16 VDD
15 SYSCLK
14 SSER
13 SMSYNC
12 SFSYNC
11 SCHCLK
10 S/P
9 SCLKSEL
16-PIN DIP (300 MIL)
16-PIN SOIC (300 MIL)
DESCRIPTION
The DS2175 is a low–power CMOS elastic–store memory optimized for use in primary rate telecommu-
nications transmission equipment. The device serves as a synchronizing element between async data
streams and is compatible with North American (T1–1.544 MHz) and European (CEPT–2.048 MHz) rate
networks. The chip has several flexible operating modes which eliminate support logic and hardware cur-
rently required to interconnect parallel or serial TDM backplanes. Application areas include digital
trunks, drop and insert equipment, digital cross–connects (DACS), private network equipment and
PABX–to–computer interfaces such as DMI and CPI.
1 of 12
092099
1 page  
RECEIVE SIDE TIMING (RCLK = 1.544 MHz) Figure 2
DS2175
RECEIVE SIDE TIMING (RCLK = 2.048 MHz) Figure 3
NOTES:
1. All channel data is passed through the elastic store in 2.048 MHz system side applications
(SCLKSEL = 1);
2. Data in channels >24 is ignored in 1.544 MHz system side applications (SCLKSEL = 0).
SYSTEM MULTIFRAME BOUNDARY TIMING (SYSCLK = 1.544 MHz) Figure 4
NOTES:
1. In 1.544 MHz receive side applications (RCLKSEL=0), the F–bit position contains F–bit data
extracted from the data stream at RSER. The F–bit position is forced to “1” in 2.048 MHz receive
side applications (RCLKSEL=1).
2. In 2.048 MHz receive side applications (RCLKSEL=1), the E–bit position is forced to “1” and data in
channels >24 is ignored.
5 of 12
5 Page 
DS2175S T1/CEPT ELASTIC STORE
DS2175
PKG
DIM
A IN.
B IN.
C IN.
E IN.
F IN.
G IN.
H IN.
J IN.
K IN.
L IN.
16-PIN
MIN MAX
0.402 0.412
0.290 0.300
0.089 0.095
0.004 0.012
0.094 0.105
0.050 BSC
0.398 0.416
0.009 0.013
0.013 0.019
0.016 0.040
11 of 12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet DS2175N.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
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