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PDF DS2156 Data sheet ( Hoja de datos )
| Número de pieza | DS2156 | |
| Descripción | T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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GENERAL DESCRIPTION
The DS2156 is a software-selectable T1, E1, or J1
single-chip transceiver (SCT) for short-haul and
long-haul applications. The backplane is user-
configurable for a TDM or UTOPIA II bus interface.
The DS2156 is composed of a line interface unit
(LIU), framer, HDLC controllers, and a
UTOPIA/TDM backplane interface, and is controlled
by an 8-bit parallel port configured for Intel or
Motorola bus operations. The DS2156 is pin and
software compatible with the DS2155.
The LIU is composed of transmit and receive
interfaces and a jitter attenuator. The transmit
interface is responsible for generating the necessary
waveshapes for driving the network and providing
the correct source impedance depending on the type
of media used. T1 waveform generation includes
DSX-1 line buildouts as well as CSU line buildouts
of -7.5dB, -15dB, and -22.5dB. E1 waveform
generation includes G.703 waveshapes for both 75Ω
coax and 120Ω twisted cables. The receive interface
provides network termination and recovers clock and
data from the network.
APPLICATIONS
Inverse Mux ATM (IMA)
T1/E1/J1 Line Cards
Switches and Routers
Add-Drop Multiplexers
DS2156
T1/E1/J1 Single-Chip Transceiver
TDM/UTOPIA II Interface
FEATURES
§ Complete T1/DS1/ISDN-PRI/J1 Transceiver
Functionality
§ Complete E1 (CEPT) PCM-30/ISDN-PRI
Transceiver Functionality
§ User-Selectable TDM or UTOPIA II Bus
Interface
§ Long-Haul and Short-Haul Line Interface for
Clock/Data Recovery and Waveshaping
§ CMI Coder/Decoder for Optical I/F
§ Crystal-Less Jitter Attenuator
§ Fully Independent Transmit and Receive
Functionality
§ Dual HDLC Controllers
§ Programmable BERT Generator and Detector
§ Internal Software-Selectable Receive and
Transmit-Side Termination Resistors for
75Ω/100Ω/120Ω T1 and E1 Interfaces
§ Dual Two-Frame Elastic-Store Slip Buffers that
Connect to Asynchronous Backplanes Up to
16.384MHz
§ 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz Clock Output Synthesized to
Recovered Network Clock
Features continued on page 8.
ORDERING INFORMATION
PART
DS2156L
DS2156LN
TEMP RANGE
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
100 LQFP
100 LQFP
T1/E1/J1
NETWORK
DS2156
T1/E1/J1
TDM/UTOPIA
UTOPIA
BACKPLANE
TDM
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:www.maxim-ic.com/errata.
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DS2156
23.3.2 Transmit Open-Circuit Detector.........................................................................................................151
23.3.3 Transmit BPV Error Insertion ............................................................................................................151
23.3.4 Transmit G.703 Synchronization Signal (E1 Mode)...........................................................................151
23.4 MCLK PRESCALER .................................................................................................................................152
23.5 JITTER ATTENUATOR...............................................................................................................................152
23.6 CMI (CODE MARK INVERSION) OPTION.................................................................................................152
FIGURE 23-2. CMI CODING ..................................................................................................................................152
23.7 LIU CONTROL REGISTERS ......................................................................................................................153
23.8 RECOMMENDED CIRCUITS.......................................................................................................................160
FIGURE 23-3. BASIC INTERFACE ...........................................................................................................................160
FIGURE 23-4. PROTECTED INTERFACE USING INTERNAL RECEIVE TERMINATION ..............................................161
23.9 COMPONENT SPECIFICATIONS.................................................................................................................162
TABLE 23-A. TRANSFORMER SPECIFICATIONS .....................................................................................................162
FIGURE 23-5. E1 TRANSMIT PULSE TEMPLATE ....................................................................................................163
FIGURE 23-6. T1 TRANSMIT PULSE TEMPLATE ....................................................................................................163
FIGURE 23-7. JITTER TOLERANCE.........................................................................................................................164
FIGURE 23-8. JITTER TOLERANCE (E1 MODE)......................................................................................................164
FIGURE 23-9. JITTER ATTENUATION (T1 MODE)..................................................................................................165
FIGURE 23-10. JITTER ATTENUATION (E1 MODE)................................................................................................165
FIGURE 23-11. OPTIONAL CRYSTAL CONNECTIONS .............................................................................................166
24. UTOPIA BACKPLANE INTERFACE ...................................................................................................167
24.1 DESCRIPTION ...........................................................................................................................................167
24.1.1 List of Applicable Standards...............................................................................................................167
24.1.2 Acronyms and Definitions...................................................................................................................167
24.2 UTOPIA CLOCK MODES.........................................................................................................................168
FIGURE 24-1. UTOPIA CLOCKING CONFIGURATIONS .........................................................................................168
24.3 FULL T1/E1 MODE AND CLEAR-CHANNEL E1 MODE ............................................................................168
24.4 FRACTIONAL T1/E1 MODE ......................................................................................................................169
TABLE 24-A. UTOPIA CLOCK MODE CONFIGURATION ......................................................................................169
24.5 TRANSMIT OPERATION............................................................................................................................170
24.5.1 UTOPIA Side Transmit: Muxed Mode with One Transmit CLAV ......................................................170
FIGURE 24-2. POLLING PHASE AND SELECTION PHASE AT TRANSMIT INTERFACE..............................................171
FIGURE 24-3. END AND RESTART OF CELL AT TRANSMIT INTERFACE................................................................172
FIGURE 24-4. TRANSMISSION TO PHY PAUSED FOR THREE CYCLES...................................................................173
24.5.2 UTOPIA Side Transmit: Direct Status Mode (Multitransmit CLAV) .................................................173
FIGURE 24-5. EXAMPLE OF DIRECT STATUS INDICATION, TRANSMIT DIRECTION ..............................................174
24.5.3 Transmit Processing ...........................................................................................................................175
FIGURE 24-6. TRANSMIT CELL FLOW ...................................................................................................................175
24.6 RECEIVE OPERATION...............................................................................................................................176
24.6.1 Receive Processing .............................................................................................................................176
FIGURE 24-7. CELL-DELINEATION STATE DIAGRAM ...........................................................................................176
FIGURE 24-8. HEADER CORRECTION STATE MACHINE ........................................................................................177
24.6.2 UTOPIA Side Receive: Muxed Mode with One Receive CLAV ..........................................................178
FIGURE 24-9. POLLING PHASE AND SELECTION AT RECEIVE INTERFACE ............................................................178
FIGURE 24-10. END AND RESTART OF CELL TRANSMISSION AT RECEIVE INTERFACE ........................................179
24.6.3 UTOPIA Side Receive: Direct Status Mode (Multireceive CLAV) .....................................................179
FIGURE 24-11. EXAMPLE OF DIRECT STATUS INDICATION, RECEIVE DIRECTION ...............................................180
24.7 REGISTER DEFINITIONS ...........................................................................................................................181
24.8 RECEIVE FIFO OVERRUN........................................................................................................................192
24.9 UTOPIA DIAGNOSTIC LOOPBACK..........................................................................................................192
25. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION........................193
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DS2156
2. DETAILED DESCRIPTION
The DS2156 is a software-selectable T1, E1, or J1 single-chip transceiver (SCT) for short-haul and long-
haul applications. The backplane is user-configurable for a TDM or UTOPIA II bus interface. The
DS2156 is composed of an LIU, framer, HDLC controllers, and a UTOPIA/TDM backplane interface,
and is controlled by an 8-bit parallel port configured for Intel or Motorola bus operations. The DS2156 is
pin and software compatible with the DS2155.
The LIU is composed of transmit and receive interfaces and a jitter attenuator. The transmit interface is
responsible for generating the necessary waveshapes for driving the network and providing the correct
source impedance depending on the type of media used. T1 waveform generation includes DSX-1 line
buildouts as well as CSU line buildouts of -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes
G.703 waveshapes for both 75Ω coax and 120Ω twisted cables. The receive interface provides network
termination and recovers clock and data from the network. The receive sensitivity adjusts automatically to
the incoming signal and can be programmed for 0 to 43dB or 0 to 12dB for E1 applications and 0 to 30dB
or 0 to 36dB for T1 applications. The jitter attenuator removes phase jitter from the transmitted or
received signal. The crystal-less jitter attenuator requires only a 2.048MHz MCLK for both E1 and T1
applications (with the option of using a 1.544MHz MCLK in T1 applications) and can be placed in either
transmit or receive data paths. An additional feature of the LIU is a CMI coder/decoder for interfacing to
optical networks.
On the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane
interface section. The framer inserts the appropriate synchronization framing patterns, alarm information,
calculates and inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression) and AMI
line coding. The receive-side framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes to the
data stream, reports alarm information, counts framing/coding/CRC errors, and provides clock/data and
frame-sync signals to the backplane interface section.
Both the transmit and receive path have two HDLC controllers. The HDLC controllers transmit and
receive data through the framer block. The HDLC controllers can be assigned to any time slot, group of
time slots, portion of a time slot or to FDL (T1) or Sa bits (E1). Each controller has 128-byte FIFOs, thus
reducing the amount of processor overhead required to manage the flow of data. In addition, built-in
support for reducing the processor time is required in SS7 applications.
The backplane interface provides a versatile method of sending and receiving data from the host system.
Elastic stores provide a method for interfacing to asynchronous systems, converting from a T1/E1
network to a 2.048MHz, 4.096MHz, 8.192MHz, or N x 64kHz system backplane. The elastic stores also
manage slip conditions (asynchronous interface). An interleave bus option (IBO) is provided to allow up
to eight transceivers to share a high-speed backplane in TDM mode.
The parallel port provides access for control and configuration of the DS2156’s features. The extended
system information bus (ESIB) function allows up to eight transceivers to be accessed by a single read for
interrupt status or other user-selectable alarm status information. Diagnostic capabilities include
loopbacks, PRBS pattern generation/detection, and 16-bit loop-up and loop-down code generation and
detection.
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DS2156.PDF ] | |
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