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PDF DS2154L Data sheet ( Hoja de datos )

Número de pieza DS2154L
Descripción Enhanced E1 Single Chip Transceiver
Fabricantes Dallas Semiconducotr 
Logotipo Dallas Semiconducotr Logotipo



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www.dalsemi.com
DS2154
Enhanced E1 Single Chip Transceiver
FEATURES
Complete E1(CEPT) PCM-30/ISDN-PRI
transceiver functionality
Onboard long- and short-haul line interface for
clock/data recovery and waveshaping
32-bit or 128-bit crystal-less jitter attenuator
Generates line build outs for both 120=and
75=lines
Frames to FAS, CAS, and CRC4 formats
Dual onboard two-frame elastic store slip buffers
that can connect to asynchronous backplanes up to
8.192 MHz
8-bit parallel control port that can be used directly
on either multiplexed or non-multiplexed buses
Extracts and inserts CAS signaling
Detects and generates Remote and AIS alarms
Programmable output clocks for Fractional E1,
H0, and H12 applications
Fully independent transmit and receive
functionality
Full access to both Si and Sa bits aligned with
CRC multiframe
Four separate loopbacks for testing functions
Large counters for bipolar and code violations,
CRC4 codeword errors, FAS errors, and E bits
Pin compatible with DS2152 T1 Enhanced Single-
Chip Transceiver
5V supply; low power CMOS
100-pin 14mm2 body LQFP package
PACKAGE OUTLINE
1
ORDERING INFORMATION
DS2154L
(0°C to 70°C)
DS2154LN
(-40°C to +85°C)
DESCRIPTION
The DS2154 Enhanced Single-Chip Transceiver (ESCT) contains all of the necessary functions for
connection to E1 lines. The device is an upward compatible version of the DS2153 Single-Chip
Transceiver. The onboard clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to a NRZ
serial stream. The DS2154 automatically adjusts to E1 22AWG (0.6 mm) twisted-pair cables from 0 to
over 2 km in length. The device can generate the necessary G.703 waveshapes for both 75-ohm coax and
120-ohm twisted cables. The onboard jitter attenuator (selectable to either 32 bits or 128 bits) can be
placed in either the transmit or receive data paths. The framer locates the frame and multiframe
boundaries and monitors the data stream for alarms. It is also used for extracting and inserting signaling
data, Si, and Sa bit information. The device contains a set of internal registers which the user can access
to control the operation of the unit. Quick access via the parallel control port allows a single controller to
handle many E1 lines. The device fully meets all of the latest E1 specifications including ITU G.703,
G.704, G.706, G.823, G.932, and I.431 as well as ETS 300 011, 300 233, 300 166, TBR 12 and TBR 13.
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DS2154L pdf
DS2154 ENHANCED E1 SINGLE-CHIP TRANSCEIVER Figure 1-1
DS2154
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DS2154L arduino
DS2154
Transmit Data [TDATA]. Sampled on the falling edge of TCLK with data to be clocked through the
transmit side formatter. This pin is normally tied to TESO.
Transmit Positive Data Output [TPOSO]. Updated on the rising edge of TCLKO with the bipolar data
out of the transmit side formatter. Can be programmed to source NRZ data via the Output Data Format
(TCR1.7) control bit. This pin is normally tied to TPOSI.
Transmit Negative Data Output [TNEGO]. Updated on the rising edge of TCLKO with the bipolar
data out of the transmit side formatter. This pin is normally tied to TNEGI.
Transmit Clock Output [TCLKO]. Buffered clock that is used to clock data through the transmit side
formatter (i.e. either TCLK or RCLKO if Loss Of Transmit Clock is enabled and in effect or RCLKI if
remote loopback is enabled). This pin is normally tied to TCLKI.
Transmit Positive Data Input [TPOSI]. Sampled on the falling edge of TCLKI for data to be
transmitted out onto the E1 line. Can be internally connected to TPOSO by tying the LIUC pin high.
Transmit Negative Data Input [TNEGI]. Sampled on the falling edge of TCLKI for data to be
transmitted out onto the E1 line. Can be internally connected to TNEGO by tying the LIUC pin high.
Transmit Clock Input [TCLKI]. Line interface transmit clock. Can be internally connected to TCLKO
by tying the LIUC pin high.
RECEIVE SIDE DIGITAL PINS
Receive Link Data [RLINK]. Updated with the full recovered E1 data stream on the rising edge of
RCLK.
Receive Link Clock [RLCLK]. 4 kHz to 20 kHz clock (Sa bits) for the RLINK output. See Section 11
for details.
Receive Clock [RCLK]. 2.048 MHz clock that is used to clock data through the receive side framer.
Receive Channel Clock [RCHCLK]. 256 kHz clock which pulses high during the LSB of each channel.
Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK
when the receive side elastic store is enabled. Useful for parallel to serial conversion of channel data.
Receive Channel Block [RCHBLK]. A user-programmable output that can be forced high or low during
any of the 32 E1 channels. Synchronous with RCLK when the receive side elastic store is disabled.
Synchronous with RSYSCLK when the receive side elastic store is enabled. Useful for blocking clocks to
a serial UART or LAPD controller in applications where not all E1 channels are used such as Fractional
E1, 384k bps service, 768k bps, or ISDN-PRI. Also useful for locating individual channels in drop-and-
insert applications, for external per-channel loopback, and for per-channel conditioning. See Section 9 for
details.
Receive Serial Data [RSER]. Received NRZ serial data. Updated on rising edges of RCLK when the
receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive side
elastic store is enabled.
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