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PDF DS2152L Data sheet ( Hoja de datos )
| Número de pieza | DS2152L | |
| Descripción | Enhanced T1 Single-Chip Transceiver | |
| Fabricantes | Dallas Semiconducotr | |
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DS2152
Enhanced T1 Single-Chip Transceiver
FEATURES
§ Complete DS1/ISDN-PRI transceiver
functionality
§ Line interface can handle both long and short haul
trunks
§ 32-bit or 128-bit crystal-less jitter attenuator
§ Generates DSX-1 and CSU line build outs
§ Frames to D4, ESF, and SLC-96R formats
§ Dual onboard two-frame elastic store slip buffers
that can connect to asynchronous backplanes up to
8.192 MHz
§ 8-bit parallel control port that can be used directly
on either multiplexed or non-multiplexed buses
(Intel or Motorola)
§ Extracts and inserts robbed-bit signaling
§ Detects and generates yellow (RAI) and blue
(AIS) alarms
§ Programmable output clocks for Fractional T1
§ Fully independent transmit and receive
functionality
§ Integral HDLC controller with 16-byte buffers for
the FDL
§ Generates and detects in-band loop codes from 1
to 8 bits in length including CSU loop codes
§ Contains ANSI 1's density monitor and enforcer
§ Large path and line error counters including BPV,
CV, CRC6, and framing bit errors
§ Pin compatible with DS2154 E1 Enhanced Single-
Chip Transceiver
§ 5V supply; low power CMOS
§ 100-pin 14mm2 body LQFP package
PIN ASSIGNMENT
1
ORDERING INFORMATION
DS2152L
(0°C to 70°C)
DS2152LN
(-40°C to +85°C)
DESCRIPTION
The DS2152 T1 Enhanced Single-Chip Transceiver contains all of the necessary functions for connection
to T1 lines, whether they be DS-1 long haul or DSX-1 short haul. The clock recovery circuitry
automatically adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both
DSX-1 line build outs as well as CSU line build outs of -7.5 dB, -15 dB, and -22.5 dB. The onboard jitter
attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data
paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It
is also used for extracting and inserting robbed-bit signaling data and FDL data. The device contains a set
of internal registers which the user can access and control the operation of the unit. Quick access via the
parallel control port allows a single controller to handle many T1 lines. The device fully meets all of the
latest T1 specifications including ANSI T1.403-1995, ANSI T1.231-1993, AT&T TR 62411 (12-90),
AT&T TR54016, and ITU G.703, G.704, G.706, G.823, and I.431.
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DS2152
TTIP and TRING pins via a coupling transformer. The line driver can handle both long (CSU) and short
haul (DSX-1) lines.
Reader’s Note
This data sheet assumes a particular nomenclature of the T1 operating environment. In each 125 us frame,
there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by
channel 1. Each channel is made up of 8 bits which are numbered 1 to 8. Bit number 1 is the MSB and is
transmitted first. Bit number 8 is the LSB and is transmitted last. Throughout this data sheet, the
following abbreviations will be used:
D4
SLC-96
ESF
B8ZS
CRC
Ft
Fs
FPS
MF
BOC
HDLC
FDL
Superframe (12 frames per multiframe) Multiframe Structure
Subscriber Loop Carrier - 96 Channels (SLC-96 is an AT&T registered trademark)
Extended Superframe (24 frames per multiframe) Multiframe Structure
Bipolar with 8 0 Subsitution
Cyclical Redundancy Check
Terminal Framing Pattern in D4
Signaling Framing Pattern in D4
Framing Pattern in ESF
Multiframe
Bit Oriented Code
High Level Data Link Control
Facility Data Link
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DS2152
Receive Channel Block [RCHBLK]. A user-programmable output that can be forced high or low during
any of the 24 T1 channels. Synchronous with RCLK when the receive side elastic store is disabled.
Synchronous with RSYSCLK when the receive side elastic store is enabled. Useful for blocking clocks to
a serial UART or LAPD controller in applications where not all T1 channels are used, such as Fractional
T1, 384 kbps service, 768 kbps, or ISDN-PRI. Also useful for locating individual channels in drop-and-
insert applications, for external per-channel loopback, and for per-channel conditioning. See Section 9 for
details.
Receive Serial Data [RSER]. Received NRZ serial data. Updated on rising edges of RCLK when the
receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive side
elastic store is enabled.
Receive Sync [RSYNC]. An extracted pulse, one RCLK wide, is output at this pin which identifies either
frame (RCR2.4=0) or multiframe (RCR2.4=1) boundaries. If set to output frame boundaries then via
RCR2.5, RSYNC can also be set to output double-wide pulses on signaling frames. If the receive side
elastic store is enabled via CCR1.2, then this pin can be enabled to be an input via RCR2.3 at which a
frame or multiframe boundary pulse is applied. See Section 15 for details.
Receive Frame Sync [RFSYNC]. An extracted 8 kHz pulse 1 RCLK wide is output at this pin which
identifies frame boundaries.
Receive Multiframe Sync [RMSYNC]. Only used when the receive side elastic store is enabled. An
extracted pulse, 1 RSYSCLK wide, is output at this pin which identifies multiframe boundaries. If the
receive side elastic store is disabled, then this output will output multiframe boundaries associated with
RCLK.
Receive Data [RDATA]. Updated on the rising edge of RCLK with the data out of the receive side
framer.
Receive System Clock [RSYSCLK]. 1.544 MHz or 2.048 MHz clock. Only used when the elastic store
function is enabled. Should be tied low in applications that do not use the elastic store. Can be burst at
rates up to 8.192 MHz.
Receive Signaling Output [RSIG]. Outputs signaling bits in a PCM format. Updated on rising edges of
RCLK when the receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the
receive side elastic store is enabled.
Receive Loss of Sync / Loss of Transmit Clock [RLOS/LOTC]. A dual function output that is
controlled by the CCR3.5 control bit. This pin can be programmed to either toggle high when the
synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not been
toggled for 5 µs.
Receive Carrier Loss [RCL]. Set high when the line interface detects a loss of carrier.
Receive Signaling Freeze [RSIGF]. Set high when the signaling data is frozen via either automatic or
manual intervention. Used to alert downstream equipment of the condition.
8 MHz Clock [8MCLK]. A 8.192 MHz output clock that is referenced to the clock that is output at the
RCLK pin and is used to clock data through the receive side framer.
11 of 93
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| PDF Descargar | [ Datasheet DS2152L.PDF ] | |
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