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PDF DS21448LN Data sheet ( Hoja de datos )

Número de pieza DS21448LN
Descripción 3.3V E1/T1/J1 Quad Line Interface
Fabricantes Dallas Semiconducotr 
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DS21448
3.3V E1/T1/J1 Quad Line Interface
www.maxim-ic.com
GENERAL DESCRIPTION
The DS21448 is a quad-port E1 or T1 line interface
unit (LIU) for short-haul and long-haul applications. It
incorporates four independent transmitters and four
independent receivers in a single 144-pin PBGA or
128-pin LQFP package.
The transmit drivers generate the necessary G.703
E1 waveshapes in 75W or 120W applications and the
DSX-1 or CSU line build-outs of 0dB, -7.5dB, -15dB,
and -22.5dB for T1 applications.
The DS21448 has a usable receiver sensitivity of
0 to -43dB for E1 applications and 0 to -36dB for T1
that allows it to operate on 0.63mm (22AWG) cables
up to 2.5km (E1) and 6000ft (T1) in length. The user
has the option to use internal receive termination,
software selectable for 75W, 100W, and 120W
applications, or external termination.
The on-board crystal-less jitter attenuator can be
placed in either the transmit or the receive data path,
and requires only a 2.048MHz MCLK for both E1 and
T1 applications (with the option of using a 1.544MHz
MCLK in T1 applications).
The DS21448 has diagnostic capabilities such as
loopbacks and PRBS pattern generation and
detection. 16-bit loop-up and loop-down codes can
be generated and detected. A single input pin can
power down all transmitters to allow the
implementation of hitless protection switching (HPS)
for 1+1 redundancy without the use of relays.
The device can be controlled through an 8-bit parallel
port (muxed or nonmuxed) or a serial port, and it can
be used in hardware mode. A standard boundary
scan interface supports board-level testing.
APPLICATIONS
Integrated Multiservice Access Platforms
T1/E1 Cross-Connects, Multiplexers, and Channel
Banks
Central-Office Switches and PBX Interfaces
T1/E1 LAN/WAN Routers
Wireless Base Stations
FEATURES
§ Four Complete E1, T1, or J1 LIUs
§ Supports Long- and Short-Haul Trunks
§ Internal Software-Selectable Receive-Side
Termination for 75W/100W/120W
§ 3.3V Power Supply
§ 32-Bit or 128-Bit Crystal-Less Jitter Attenuator
Requires Only a 2.048MHz Master Clock for E1
and T1, with the Option to Use 1.544MHz for T1
§ Generates the Appropriate Line Build-Outs With
and Without Return Loss for E1, and DSX-1 and
CSU Line Build-Outs for T1
§ AMI, HDB3, and B8ZS Encoding/Decoding
§ 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz
Clock Output Synthesized to Recovered Clock
§ Programmable Monitor Mode for Receiver
§ Loopbacks and PRBS Pattern Generation/
Detection with Output for Received Errors
§ Generates/Detects In-Band Loop Codes, 1 to 16
Bits, Including CSU Loop Codes
§ 8-Bit Parallel or Serial Interface with Optional
Hardware Mode
§ Muxed and Nonmuxed Parallel Bus Supports
Intel or Motorola
§ Detects/Generates Blue (AIS) Alarms
§ NRZ/Bipolar Interface for Tx/Rx Data I/O
§ Transmit Open-Circuit Detection
§ Receive Carrier Loss (RCL) Indication (G.775)
§ High-Z State for TTIP and TRING
§ 50mARMS Transmit Current Limiter
§ JTAG Boundary Scan Test Port per IEEE 1149.1
§ Meets Latest E1 and T1 Specifications Including
ANSI.403-1999, ANSI T1.408, AT&T TR 62411,
ITU G.703, G.704, G.706, G.736, G.775, G.823,
I.431, O.151, O.161, ETSI ETS 300 166,
JTG.703, JTI.431, TBR12, TBR13, and CTR4
ORDERING INFORMATION
PART
TEMP RANGE
VOLTAGE
(V)
DS21448
0°C to +70°C
3.3
DS21448N -40°C to +85°C
3.3
DS21448L
0°C to +70°C
3.3
DS21448LN -40°C to +85°C
3.3
Pin Configurations appear in Section 11.
PIN-
PACKAGE
144 BGA
144 BGA
128 LQFP
128 LQFP
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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DS21448LN pdf
1. BLOCK DIAGRAMS
Figure 1-1. Block Diagram
CHANNEL 4
CHANNEL 3
CHANNEL 2
CHANNEL 1
DS21448 3.3V T1/E1/J1 Quad Line Interface
TYPICAL OF ALL FOUR CHANNELS
22
POWER
CONNECTIONS
RRING
RTIP
JACLK
VCO/PLL
2.048MHz TO
1.544MHz PLL
n
16.384MHz OR
8.192MHz OR
4.096MHz OR
2.048MHz
SYNTHESIZER
See Figure 1-2
TRING
TTIP
BIS0
UNFRAMED
ALL-ONES
INSERTION
MUX (THE SERIAL, PARALLEL, AND HARDWARE INTERFACES
SHARE DEVICE PINS)
MUX
See Figure 1-3
CONTROL AND TEST
PORT (ROUTED TO
ALL BLOCKS)
BPCLK
RPOS
RCLK
RNEG
PBEO
RCL/LOTC
TPOS
TCLK
TNEG
HRST
TXDIS/TEST
SERIAL
INTERFACE
PARALLEL INTERFACE
CONTROL AND
(ROUTED TO
ALL BLOCKS)
58
JTAG PORT
Dallas
Semiconductor
DS21448
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DS21448LN arduino
DS21448 3.3V T1/E1/J1 Quad Line Interface
PIN I/O
FUNCTION
BPCLK1–BPCLK4
O
Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz clock output that is
referenced to RCLK selectable through CCR5.7 and CCR5.6.
TTIP1–TTIP4
O Transmit Tip and Ring. Analog line-driver outputs. These pins connect through a step-up
TRING–TRING4
O transformer to the line. See Section 7 for details.
Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge (CCR2.0 = 1)
RPOS1–RPOS4
O
of RCLK with bipolar data out of the line interface. Set NRZE (CCR1.6) to 1 for NRZ applications.
In NRZ mode, data is output on RPOS, and a received error (BPV, CV, or EXZ) causes a
positive-going pulse synchronous with RCLK at RNEG.
Receive Negative Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge (CCR2.0 =
RNEG1–RNEG4
O
1) of RCLK with the bipolar data out of the line interface. Set NRZE (CCR1.6) to 1 for NRZ
applications. In NRZ mode, data is output on RPOS, and a received error (BPV, CV, or EXZ)
causes a positive-going pulse synchronous with RCLK at RNEG.
RCLK1–RCLK4
O
Receive Clock. Buffered recovered clock from the line. Synchronous to MCLK in absence of
signal at RTIP and RRING.
TPOS1–TPOS4
I
Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0) or the rising edge (CCR2.1 =
1) of TCLK for data to be transmitted out onto the line.
TNEG1–TNEG4
I
Transmit Negative Data. Sampled on the falling edge (CCR2.1 = 0) or the rising edge (CCR2.1 =
1) of TCLK for data to be transmitted out onto the line.
Transmit Clock. A 2.048MHz or 1.544MHz primary clock used to clock data through the transmit
TCLK1–TCLK4
I side formatter. They can be sourced internally by MCLK or RCLK. See Common Control Register
1 and Figure 1-3.
JTRST
I JTAG Reset
JTMS
I JTAG Mode Select
JTCLK
I JTAG Clock
JTDI
I JTAG Data In
JTDO
O JTAG Data Out
VSM
I Voltage Supply Mode (LQFP only). VSM should be wired low for correct operation.
TVDD1–TVDD4 — 3.3V, ±5% Transmitter Positive Supply
VDD1–VDD4
— 3.3V, ±5% Positive Supply
TVSS1–TVSS4
— Transmitter Signal Ground for Transmitter Outputs
VSS1–VSS4
— Signal Ground
Table 2-E. Hardware Interface Mode Pin Description
PIN
ETS
NRZE
SCLKE
DJA
JAMUX
JAS
HBE
L0/L1/L2
I/O FUNCTION
E1/T1 Select
I 0 = E1
1 = T1
NRZ Enable
I
0 = bipolar data at RPOS/RNEG and TPOS/TNEG
1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a positive-going pulse when the
device receives a BPV, CV, or EXZ.
Receive and Transmit Synchronization Clock Enable. SCLKE combines RSCLKE (CCR5.3) and
I
TSCLKE (CCR5.2).
0 = disable 2.048MHz synchronization transmit and receive mode
1 = enable 2.048MHz synchronization transmit and receive mode
Disable Jitter Attenuator
I 0 = jitter attenuator enabled
1 = jitter attenuator disabled
Jitter Attenuator Clock Mux. Controls the source for JACLK.
I 0 = JACLK sourced from MCLK (2.048MHz or 1.544MHz at MCLK).
1 = JACLK sourced from internal PLL (2.048 MHz at MCLK).
Jitter Attenuator Path Select
I 0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
Receive and Transmit HDB3/B8ZS Enable. HBE combines RHBE (CCR2.3) and THBE
I
(CCR2.2).
0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
I
Line Build-Out Select Bits 0,1, and 2. These pins set the transmitter build-out; see (Table 7-A
(E1) and Table 7-B (T1).
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