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PDF DS2143Q Data sheet ( Hoja de datos )

Número de pieza DS2143Q
Descripción E1/ISDN-PRI framing transceiver
Fabricantes Dallas Semiconducotr 
Logotipo Dallas Semiconducotr Logotipo



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No Preview Available ! DS2143Q Hoja de datos, Descripción, Manual

www.dalsemi.com
FEATURES
E1/ISDN-PRI framing transceiver
Frames to CAS, CCS, and CRC4 formats
Parallel control port
Onboard two frame elastic store slip buffer
Extracts and inserts CAS signaling bits
Programmable output clocks for fractional E1
links, DS0 loopbacks, and drop and insert
applications
Onboard Sa data link support circuitry
FEBE E-Bit detection, counting and
generation
Pin-compatible with DS2141A T1 Controller
5V supply; low power (50 mW) CMOS
Available in 40-pin DIP and 44-pin PLCC
(DS2143Q)
DS2143/DS2143Q
E1 Controller
PIN ASSIGNMENT
TCLK
TSER
TCHCLK
TPOS
TNEG
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
BTS
RD(DS)
CS
ALE(AS)
WR(R/W)
RLINK
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VDD
39 TSYNC
38 TLINK
37 TLCLK
36 INT1
35 INT2
34 RLOS/LOTC
33 TCHBLK
32 RCHBLK
31 LI_CS
30 LI_CLK
29 LI_SDI
28 SYSCLK
27 RNEG
26 RPOS
25 RSYNC
24 RSER
23 RCHCLK
22 RCLK
21 RLCLK
40-Pin DIP (600-mil)
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
BTS
RD(DS)
NC
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 35
12 44-PIN PLCC 34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
RLOS/LOTC
TCHBLK
RCHBLK
LI_CS
LI_CLK
LI_SDI
NC
NC
SYSCLK
RNEG
RPOS
DESCRIPTION
The DS2143 is a comprehensive, software-driven E1 framer. It is meant to act as a slave or coprocessor to
a microcontroller or microprocessor. Quick access via the parallel control port allows a single micro to
handle many E1 lines. The DS2143 is very flexible and can be configured into numerous orientations via
software. The software orientation of the device allows the user to modify their design to conform to
future E1 specification changes. The controller contains a set of 69 8-bit internal registers which the user
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DS2143Q pdf
DS2143/DS2143Q
PIN SYMBOL TYPE
DESCRIPTION
29 LI_SDI
O Serial Port Data for the Line Interface. Connects directly to the
SDI input pin on the line interface. See Sections 12 and 13 for
timing details.
30 LI_CLK
O Serial Port Clock for the Line Interface. Connects directly to the
SCLK input pin on the line interface. See Sections 12 and 13 for
timing details.
31 LI_ CS
O Serial Port Chip Select for the Line Interface. Connects directly
to the CS input pin on the line interface. See Sections 12 and 13 for
timing details.
32 RCHBLK
O Receive/Transmit Channel Block. A user programmable output
33 TCHBLK
that can be forced high or low during any of the 32 E1 channels.
Useful for blocking clocks to a serial UART or LAPD controller in
applications where not all E1 channels are used such as Fractional
E1 or ISDN-PRI. Also useful for locating individual channels in
drop-and-insert applications. See Sections 9 and 13 for details.
34 RLOS/LOTC O Receive Loss of Sync/Loss of Transmit Clock. A dual function
output. If TCR2.0=0, then this pin will toggle high when the
synchronizer is searching for the E1 frame and multiframe. If
TCR2.0=1, then this pin will toggle high if the TCLK pin has not
toggled for 5 µs.
35 INT2
O Receive Alarm Interrupt 2. Flags host controller during conditions
defined in Status Register 2. Active low, open drain output.
36 INT1
O Receive Alarm Interrupt 1. Flags host controller during alarm
conditions defined in Status Register 1. Active low, open drain
output.
37 TLCLK
O Transmit Link Clock. 4 kHz to 20 kHz demand clock for the
TLINK input. Controlled by TCR2. See Section 13 for timing
details.
38 TLINK
I Transmit Link Data. If enabled, this pin will be sampled on the
falling edge of TCLK to insert Sa bits. See Section 13 for timing
details.
39 TSYNC I/O Transmit Sync. A pulse at this pin will establish either frame or
CAS multiframe boundaries for the DS2143. Via TCR1.1, the
DS2143 can be programmed to output either a frame or multiframe
pulse at this pin. See Section 13 for timing details.
40 VDD
- Positive Supply. 5.0 volts.
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DS2143Q arduino
TCR1: TRANSMIT CONTROL REGISTER 1 (Address=12 Hex)
(MSB)
ODF
TFPT
T16S
TUA1
TSiS
TSA1
TSM
DS2143/DS2143Q
(LSB)
TSIO
SYMBOL
ODF
TFPT
T16S
TUA1
TSiS
TSA1
TSM
TSIO
POSITION NAME AND DESCRIPTION
TCR1.7
Output Data Format.
0 = bipolar data at TPOS and TNEG.
1 = NRZ data at TPOS; TNEG=0.
TCR1.6
Transmit Timeslot 0 Pass Through.
0 = FAS bits/Sa bits/Remote Alarm sourced internally from the
TAF and TNAF registers.
1 = FAS bits/Sa bits/Remote Alarm sourced from TSER.
TCR1.5
Transmit Timeslot 16 Data Select.
0 = sample timeslot 16 at TSER pin.
1 = source timeslot 16 from TS1 to TS16 registers.
TCR1.4
Transmit Unframed All 1s.
0 = transmit data normally.
1 = transmit an unframed all 1s code at TPOS and TNEG.
TCR1.3
Transmit International Bit Select.
0 = sample Si bits at TSER pin.
1 = source Si bits from TAF and TNAF registers (in this mode,
TCR1.6 must be set to 0).
TCR1.2
Transmit Signaling All 1s.
0 = normal operation.
1 = force timeslot 16 in every frame to all 1s.
TCR1.1
TSYNC Mode Select.
0 = frame mode (see the timing in Section 13).
1 = CAS and CRC4 multiframe mode (see the timing in Section
13).
TCR1.0
TSYNC I/O Select.
0 = TSYNC is an input.
1 = TSYNC is an output.
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