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PDF EPM7160E Data sheet ( Hoja de datos )

Número de pieza EPM7160E
Descripción Programmable Logic Device Family
Fabricantes Altera Corporation 
Logotipo Altera Corporation Logotipo



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December 2002, ver. 6.5
®
MAX 7000
Programmable Logic
Device Family
Data Sheet
Features...
f
High-performance, EEPROM-based programmable logic devices
(PLDs) based on second-generation MAX® architecture
5.0-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in
MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S
devices
Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S
devices with 128 or more macrocells
Complete EPLD family with logic densities ranging from 600 to
5,000 usable gates (see Tables 1 and 2)
5-ns pin-to-pin logic delays with up to 175.4-MHz counter
frequencies (including interconnect)
PCI-compliant devices available
For information on in-system programmable 3.3-V MAX 7000A or 2.5-V
MAX 7000B devices, see the MAX 7000A Programmable Logic Device Family
Data Sheet or the MAX 7000B Programmable Logic Device Family Data
Sheet.
Table 1. MAX 7000 Device Features
Feature EPM7032
Usable
gates
Macrocells
Logic array
blocks
Maximum
user I/O pins
tPD (ns)
tSU (ns)
tFSU (ns)
tCO1 (ns)
fCNT (MHz)
600
32
2
36
6
5
2.5
4
151.5
EPM7064
1,250
64
4
68
6
5
2.5
4
151.5
EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E
1,800
2,500
3,200
3,750
5,000
96 128 160 192 256
6 8 10 12 16
76 100 104 124 164
7.5
6
3
4.5
125.0
7.5
6
3
4.5
125.0
10
7
3
5
100.0
12
7
3
6
90.9
12
7
3
6
90.9
Altera Corporation
DS-MAX7000-6.5
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EPM7160E pdf
MAX 7000 Programmable Logic Device Family Data Sheet
The MAX 7000 architecture supports 100% TTL emulation and
high-density integration of SSI, MSI, and LSI logic functions. The
MAX 7000 architecture easily integrates multiple devices ranging from
PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 7000 devices
are available in a wide range of packages, including PLCC, PGA, PQFP,
RQFP, and TQFP packages. See Table 5.
Table 5. MAX 7000 Maximum User I/O Pins Note (1)
Device
44- 44- 44- 68- 84- 100- 100- 160-
Pin Pin Pin Pin Pin Pin Pin Pin
PLCC PQFP TQFP PLCC PLCC PQFP TQFP PQFP
EPM7032 36 36 36
EPM7032S 36
36
EPM7064 36
36 52 68 68
EPM7064S 36 36 68 68
EPM7096
52 64 76
EPM7128E
68 84
100
EPM7128S
68 84 84 (2) 100
EPM7160E
64 84
104
EPM7160S
64 84 (2) 104
EPM7192E
124
EPM7192S
124
EPM7256E
132 (2)
EPM7256S
160-
Pin
PGA
124
192- 208- 208-
Pin Pin Pin
PGA PQFP RQFP
164 164
164 (2) 164
Notes:
(1) When the JTAG interface in MAX 7000S devices is used for either boundary-scan testing or for ISP, four I/O pins
become JTAG pins.
(2) Perform a complete thermal analysis before committing a design to this device package. For more information, see
the Operating Requirements for Altera Devices Data Sheet.
MAX 7000 devices use CMOS EEPROM cells to implement logic
functions. The user-configurable MAX 7000 architecture accommodates a
variety of independent combinatorial and sequential logic functions. The
devices can be reprogrammed for quick and efficient iterations during
design development and debug cycles, and can be programmed and
erased up to 100 times.
Altera Corporation
5

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EPM7160E arduino
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Each programmable register can be clocked in three different modes:
By a global clock signal. This mode achieves the fastest clock-to-
output performance.
By a global clock signal and enabled by an active-high clock
enable. This mode provides an enable on each flipflop while still
achieving the fast clock-to-output performance of the global
clock.
By an array clock implemented with a product term. In this
mode, the flipflop can be clocked by signals from buried
macrocells or I/O pins.
In EPM7032, EPM7064, and EPM7096 devices, the global clock signal
is available from a dedicated clock pin, GCLK1, as shown in Figure 1.
In MAX 7000E and MAX 7000S devices, two global clock signals are
available. As shown in Figure 2, these global clock signals can be the
true or the complement of either of the global clock pins, GCLK1 or
GCLK2.
Each register also supports asynchronous preset and clear functions.
As shown in Figures 3 and 4, the product-term select matrix allocates
product terms to control these operations. Although the
product-term-driven preset and clear of the register are active high,
active-low control can be obtained by inverting the signal within the
logic array. In addition, each register clear function can be
individually driven by the active-low dedicated global clear pin
(GCLRn). Upon power-up, each register in the device will be set to a
low state.
All MAX 7000E and MAX 7000S I/O pins have a fast input path to a
macrocell register. This dedicated path allows a signal to bypass the
PIA and combinatorial logic and be driven to an input D flipflop with
an extremely fast (2.5 ns) input setup time.
Expander Product Terms
Although most logic functions can be implemented with the five
product terms available in each macrocell, the more complex logic
functions require additional product terms. Another macrocell can
be used to supply the required logic resources; however, the
MAX 7000 architecture also allows both shareable and parallel
expander product terms (“expanders”) that provide additional
product terms directly to any macrocell in the same LAB. These
expanders help ensure that logic is synthesized with the fewest
possible logic resources to obtain the fastest possible speed.
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