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PDF EP7312-IR-C Data sheet ( Hoja de datos )

Número de pieza EP7312-IR-C
Descripción HIGH-PERFORMANCE/ LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE
Fabricantes ETC 
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EP7312 Data Sheet
FEATURES
I ARM®720T Processor
— ARM7TDMI CPU operating at speeds of 74 and 90
MHz
— 8 KBytes of four-way set-associative cache
— MMU with 64-entry TLB
— Thumb code support enabled
I Ultra low power
— 90 mW at 74 MHz typical
— 108 mW at 90 MHz typical
— <.03 mW in the Standby State
I Advanced audio decoder/decompression capability
— Supports bit streams with adaptive bit rates
— Allows for support of multiple audio
decompression algorithms (MP3, WMA, AAC,
Audible, etc.)
High-Performance,
Low-Power System on Chip with
SDRAM and Enhanced Digital
Audio Interface
OVERVIEW
The Cirrus LogicEP7312 is designed for ultra-low-
power portable and line-powered applications such as
portable consumer entertainment devices, home and car
audio juke box systems, and general purpose industrial
control applications, or any device that features the
added capability of digital audio compression &
decompression. The core-logic functionality of the device
is built around an ARM720T processor with 8 KBytes of
four-way set-associative unified cache and a write buffer.
Incorporated into the ARM720T is an enhanced memory
management unit (MMU) which allows for support of
sophisticated operating systems like Microsoft®
Windows® CE and Linux®.
BLOCK DIAGRAM
(cont.)
(cont.)
D ig ita l
A u d io
In terfa ce
S erial
In terfa ce
Power
M an ag em ent
(2) UARTs
w/ IrDA
Boot
ROM
Internal Data Bus
EPB Bus
ARM720T
IC E -J T A G
ARM7TDMI CPU Core
8 KB
Cache
W rite
B u ffe r
MMU
Bus
Bridge
M averickKeyTM
M em ory Controller
SRAM I/F
SDRAM I/F
On-chip SRAM
48 KB
Clocks &
Tim ers
In terru p ts ,
P W M & G P IO
Keypad&
Touch
S creen I/F
LCD
C o n tro lle r
http://www.cirrus.com
MEMORY and STORAGE
©Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
Nov ’03
DS508PP5

1 page




EP7312-IR-C pdf
List of Figures
EP7312
High-Performance, Low-Power System on Chip
Figure 1. A Fully-Configured EP7312-Based System ................................................................................................... 12
Figure 2. Legend for Timing Diagrams ......................................................................................................................... 15
Figure 3. SDRAM Load Mode Register Cycle Timing Measurement ............................................................................ 17
Figure 4. SDRAM Burst Read Cycle Timing Measurement .......................................................................................... 18
Figure 5. SDRAM Burst Write Cycle Timing Measurement .......................................................................................... 19
Figure 6. SDRAM Refresh Cycle Timing Measurement ................................................................................................ 20
Figure 7. Static Memory Single Read Cycle Timing Measurement ...............................................................................22
Figure 8. Static Memory Single Write Cycle Timing Measurement ...............................................................................23
Figure 9. Static Memory Burst Read Cycle Timing Measurement ................................................................................ 24
Figure 10. Static Memory Burst Write Cycle Timing Measurement .............................................................................. 25
Figure 11. SSI1 Interface Timing Measurement ........................................................................................................... 26
Figure 12. SSI2 Interface Timing Measurement ........................................................................................................... 27
Figure 13. LCD Controller Timing Measurement .......................................................................................................... 28
Figure 14. JTAG Timing Measurement ......................................................................................................................... 29
Figure 15. 208-Pin LQFP Package Outline Drawing .................................................................................................... 30
Figure 16. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram .......................................................................... 31
Figure 17. 204-Ball TFBGA Package ............................................................................................................................38
Figure 18. 256-Ball PBGA Package .............................................................................................................................. 46
List of Tables
Table 1. Power Management Pin Assignments ..............................................................................................................6
Table 2. Static Memory Interface Pin Assignments ........................................................................................................6
Table 3. SDRAM Interface Pin Assignments ..................................................................................................................7
Table 4. Universal Asynchronous Receiver/Transmitters Pin Assignments ...................................................................7
Table 5. DAI Interface Pin Assignments .........................................................................................................................7
Table 6. CODEC Interface Pin Assignments ..................................................................................................................8
Table 7. SSI2 Interface Pin Assignments .......................................................................................................................8
Table 8. Serial Interface Pin Assignments ......................................................................................................................8
Table 9. LCD Interface Pin Assignments ........................................................................................................................8
Table 10. Keypad Interface Pin Assignments .................................................................................................................9
Table 11. Interrupt Controller Pin Assignments ..............................................................................................................9
Table 12. Real-Time Clock Pin Assignments ..................................................................................................................9
Table 13. PLL and Clocking Pin Assignments ................................................................................................................9
Table 14. DC-to-DC Converter Interface Pin Assignments ...........................................................................................10
Table 15. General Purpose Input/Output Pin Assignments .......................................................................................... 10
Table 16. Hardware Debug Interface Pin Assignments ................................................................................................ 10
Table 17. LED Flasher Pin Assignments ...................................................................................................................... 10
Table 18. DAI/SSI2/CODEC Pin Multiplexing ............................................................................................................... 11
Table 19. Pin Multiplexing .............................................................................................................................................11
Table 20. 208-Pin LQFP Numeric Pin Listing ............................................................................................................... 32
Table 21. 204-Ball TFBGA Ball Listing ......................................................................................................................... 40
Table 22. 256-Ball PBGA Ball Listing ........................................................................................................................... 49
Table 23. JTAG Boundary Scan Signal Ordering .........................................................................................................54
Table 24. Acronyms and Abbreviations ........................................................................................................................ 60
Table 25. Unit of Measurement ..................................................................................................................................... 60
Table 26. Pin Description Conventions ......................................................................................................................... 61
DS508PP5
©Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
5

5 Page





EP7312-IR-C arduino
EP7312
High-Performance, Low-Power System on Chip
Pin Multiplexing
Table 18 shows the pin multiplexing of the DAI, SSI2 and
the CODEC. The selection between SSI2 and the CODEC
is controlled by the state of the SERSEL bit in SYSCON2.
The choice between the SSI2, CODEC, and the DAI is
controlled by the DAISEL bit in SYSCON3 (see the
EP7312 User’s Manual for more information).
Table 18. DAI/SSI2/CODEC Pin Multiplexing
Pin
Mnemonic
I/O
DAI
SSI2 CODEC
SSICLK
SSITXDA
SSIRXDA
SSITXFR
SSIRXFR
BUZ
I/O
SCLK
SSICLK PCMCLK
O SDOUT SSITXDA PCMOUT
I
SDIN
SSIRXDA PCMIN
I/O
LRCK
SSITXFR PCMSYNC
I MCLKIN SSIRXFR p/u
O MCLKOUT
Table 19 shows the pins that have been multiplexed in
the EP7312.
Table 19. Pin Multiplexing
Signal
Block
Signal
Block
nMOE
nMWE
WRITE
A[27:15]
A[14:13]
PD[7:6]
RUN
nMEDCHG
PD[0]
PE[1:0]
PE[2]
Static Memory
Static Memory
Static Memory
Static Memory
Static Memory
GPIO
System
Configuration
Interrupt
Controller
GPIO
GPIO
GPIO
nSDCAS
SDRAM
nSDWE
SDRAM
nSDRAS
SDRAM
DRA[0:12]
SDRAM
DRA[13:14]
SDRAM
SDQM[1:0]
SDRAM
CLKEN
System
Configuration
nBROM
Boot ROM
select
LEDFLSH
LED Flasher
BOOTSEL[1:0]
System
Configuration
CLKSEL
System
Configuration
DS508PP5
©Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
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