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PDF FAN6555 Data sheet ( Hoja de datos )
| Número de pieza | FAN6555 | |
| Descripción | 2A DDR Bus Termination Regulator | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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FAN6555
2A DDR Bus Termination Regulator
www.fairchildsemi.com
Features
• Can source and sink up to 2A continous, 3A peak
• No heatsink required
• Integrated Power MOSFETs
• Generates termination voltages for DDR SDRAM
• VREF input available for external voltage divider
• Separate voltages for VCCQ and PVDD
• Buffered VREF output
• VOUT of ±3% or less at 2A
• Minimum external components
• 16-pin SOIC package
• -40°C to +85°C operating temperature range
• Shutdown for standby or suspend mode operation
• Thermal Shutdown ≈ 130ºC
Description
The FAN6555 switching regulator is designed to convert
voltage supplies ranging from 2.3V to 4V into a desired out-
put voltage or termination voltage for DDR SDRAM mem-
ory. The FAN6555 can be implemented to produce regulated
output voltages in two different modes. In the default mode,
when the VREF pin is open, the FAN6555 output voltage is
50% of the voltage applied to VCCQ. The FAN6555 can also
be used to produce various user-defined voltages by forcing a
voltage on the VREFIN pin. In this case, the output voltage
follows the input VREFIN voltage. The switching regulator
is capable of sourcing or sinking up to 2A of current while
regulating an output VTT voltage to within 3% or less.
Transient output currents of ±3A can also be accommodated.
The FAN6555 can also be used in conjunction with series
termination resisitors to provide an excellent voltage source
for active termination schemes of high speed transmission
lines as those seen in high speed memory buses and distrib-
uted backplane designs.
Block Diagram
15 16
14
VCCQ AVCC VREFOUT
200kΩ
VREFIN
11
200kΩ
AGND
13
–
+
VREF BUFFER
OSCILLATOR/
RAMP
GENERATOR
+ ERROR AMP
–
VFB
10
1
VDD
9
VDD
12
SHDN
27
PVDD1 PVDD2
VL1
(VOUT)
3
SQ
–
R
+
RAMP
COMPARATOR
Q
6
VL2
(VOUT)
DGND
8
PGND1 PGND2
45
REV. 1.1.3 8/4/03
1 page  
PRODUCT SPECIFICATION
FAN6555
Applications
Using the FAN6555 for DDR Bus Termination
The circuit schematic in Figure 1 shows a recommended
approach for constructing a bus terminating solution for a
DDR bus. This circuit can be used in PC memory and Graph-
ics memory applications as shown in Figures 3 and 4. Note
that the FAN6555 can provide the voltage reference (VREF)
and terminating voltages (VTT). Using the layout
as shown in Figures 5, 6, and 7, and measuring the VTT
performance using the test setup as described in Figure 8,
the FAN6555 delivered a VTT ± 20mV for 1A to 2A loads
(see Figure 9). Table 1 provides a recommended parts list.
An alternate application circuit for the FAN6555 is shown in
Figure 2. The number of external components is reduced
compared to the circuit in Figure 1. This is achieved by
replacing four, 0.1µF bypass capacitors with one, low ESR,
10µF ceramic capacitor placed right next to U1. Two 100Ω
resistors are also eliminated. High value, surface-mount
MLC capacitors were not available when the original appli-
cation circuit (Figure 1) was developed. Both application
circuits offer the same electrical performance but the circuit
shown in Figure 2 has a reduced bill-of-materials. Table 2
shows the recommended parts list for the circuit of Figure 2.
Bus Termination Solutions for Others Buses
Table 3 provides a summary of various bus termination VREF
& VTT requirements. The FAN6555 can be used for those
applications.
2.5V TO 4V
VTT
TO SDRAMS
GND
C1
820µF
F2V
OS-CON
L1 3.3µH
C3 10µF
C2
0.1µF
U1
FAN6555
1
VDD
2
PVDD1
3
VL1
4
PGND1
5 PGND2
6
VL2
7
PVDD2
8
DGND
16
AVCC
15
VCCQ
14
VREFOUT
13
AGND
12
SHDN
11
VREFIN
10
VFB
9
VDD
R1 100kΩ
R2 1kΩ
C4 1nF
R3
100kΩ
Figure 2. Alternate Application Circuit
C5
470µF
VCCQ
VREFOUT
SHDN
VREFIN
GND
REV. 1.1.3 8/4/03
5
5 Page 
PRODUCT SPECIFICATION
Mechanical Dimensions Inches (Millimeters)
Package: M16 16-Pin SOIC
FAN6555
Symbol
A
A1
B
C
D
E
e
H
h
L
N
α
ccc
Inches
Min. Max.
.053 .069
.004 .010
.013 .020
.0075 .010
.386 .394
.150 .158
.050 BSC
.228 .244
.010 .020
.016 .050
16
0° 8°
— .004
Millimeters
Min. Max.
1.35 1.75
0.10 0.25
0.33 0.51
0.19 0.25
9.80 10.00
3.81 4.00
1.27 BSC
5.80 6.20
0.25 0.50
0.40 1.27
16
0° 8°
— 0.10
Notes
5
2
2
3
6
Notes:
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
2. "D" and "E" do not include mold flash. Mold flash or
protrusions shall not exceed .010 inch (0.25mm).
3. "L" is the length of terminal for soldering to a substrate.
4. Terminal numbers are shown for reference only.
5. "C" dimension does not include solder finish thickness.
6. Symbol "N" is the maximum number of terminals.
16 9
EH
1
A
e
8
D
B
A1
SEATING – C –
PLANE LEAD COPLANARITY
ccc C
α
h x 45°
C
L
REV. 1.1.3 8/4/03
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet FAN6555.PDF ] | |
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