PDF FAN5240 Data sheet ( Hoja de datos )

Número de pieza	FAN5240
Descripción	Multi-Phase PWM Controller for AMD Mobile Athlon TM and Duron TM
Fabricantes	Fairchild Semiconductor
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No Preview Available ! www.fairchildsemi.com FAN5240 Multi-Phase PWM Controller for AMD Mobile AthlonTM and DuronTM Features • CPU Core power: 0.925V to 2.0V output range • ±1% reference precision over temperature • Dynamic voltage setting with 5-bit DAC • 5V to 24V input voltage range • 2 phase interleaved switching • Active droop to reduce output capacitor size • Differential remote voltage sense • High efﬁciency: >90% efﬁciency over wide load range >80% efﬁciency at light load • Excellent dynamic response with Voltage Feed-Forward and Average Current Mode control • Dynamic duty cycle clamp minimizes inductor current build up • Lossless current sensing on low-side MOSFET or Precision current sensing using sense resistor • Fault protections: Over-voltage, Over-current, and Thermal Shut-down • Controls: Enable, Forced PWM, Power Good, Power Good Delay • QSOP28, TSSOP28 Applications • AMD Mobile Athlon CPU VCORE Regulator • AMD Mobile Duron CPU VCORE Regulator General Description The FAN5240 is a single output 2-Phase synchronous buck controller to power AMD’s mobile CPU core. The FAN5240 includes a 5-bit digital-to-analog converter (DAC) that adjusts the core PWM output voltage from 0.925VDC to 2.0VDC, which may be changed during operation. Special measures are taken to allow the output to transition with controlled slew rate to comply with AMD’s Power Now technology. The FAN5240 includes a precision reference, and a proprietary architecture with integrated compensation providing excellent static and dynamic core voltage regula- tion. The regulator includes special circuitry which balances the 2 phase currents for maximum efﬁciency. At light loads, when the ﬁlter inductor current becomes discontinuous, the controller operates in a hysteretic mode, dramatically improving system efﬁciency. The hysteretic mode of operation can be inhibited by the FPWM control pin. The FAN5240 monitors the output voltage and issues a PGOOD (Power-Good) when soft start is completed and the output is in regulation. A pin is provided to add delay to PGOOD with an external capacitor. A built-in over-voltage protection (OVP) forces the lower MOSFET on to prevent the output from exceeding a set voltage. The PWM controller's overcurrent circuitry moni- tors the converter load by sensing the voltage drop across the lower MOSFET. The overcurrent threshold is set by an exter- nal resistor. If precision overcurrent protection is required, an optional external current-sense resistor may be used. REV. 1.1.7 8/29/02 1 page PRODUCT SPECIFICATION FAN5240 Electrical Speciﬁcations (VCC = 5V, VIN = 6V–24V, and TA = recommended operating ambient temperature range using circuit of Figure 1, unless otherwise noted.) Parameter Conditions Min. Typ. Max. Units Power Supplies VCC Current Operating, CL = 10pF 2 mA Shut-down (EN=0) 1 10 µA VIN Current Operating 25 µA Shut-down (EN=0) 1 µA UVLO Threshold Rising VCC 4.3 4.45 4.6 V Falling VCC 3.8 3.95 4.10 V Regulator / Control Functions Output voltage per Table 2 0.925 2.00 V Error Amplifier Gain 86 dB Error Amplifier GBW 2.7 MHz Error Amplifier Slew Rate 1 V/µS VCORE+ Input Current 25 30 35 µA ILIM Voltage RILIM = 30KΩ 0.89 0.91 V ILIM THOLDOFF CDELAY = 22nF 1.16 mS Over-voltage Threshold 2.2 2.35 2.5 V Over-voltage Protection delay 2 µS EN, input threshold Logic LOW 0.8 V Logic HIGH 2V Phase to Phase current mismatch IC contribution only Guaranteed by design ±5 % Over-Temperature Shut-down 150 °C Over-Temperature Hysteresis 25 °C Output Drivers (note 1) HDRV Output Resistance Sourcing 3.8 5 Ω Sinking 1.6 3 Ω LDRV Output Resistance Sourcing 3.8 5 Ω Sinking 0.8 1.5 Ω Oscillator Frequency 255 300 345 KHz Ramp Amplitude, pk–pk VIN = 16V 2V Ramp Offset 0.5 V Ramp Gain Reference, DAC and Soft-Start R-----a----m-----p----A----m------p---l--i--t--u---d----e-- VIN 125 mV/V VID input threshold Logic LOW 0.8 V Logic HIGH 2.0 V VID pull-up current to VCC 1 µA DAC output accuracy –1 1 % Soft Start Charging current (ISS) VSS < 90% of Programmed output 20 27 34 µA VSS > 90% of Programmed output 350 500 650 µA Note 1: Guaranteed by slew rate testing. REV. 1.1.7 8/29/02 5 5 Page PRODUCT SPECIFICATION FAN5240 Additionally, the CPU power dissipation is also slightly reduced as it is proportional to the applied voltage squared and even slight voltage decrease translates to a measurable reduction in power dissipated. ILOAD Vout (no droop) Vout droop ≈ ESR upper lim VES lower lim upper lim VES lower lim Figure 7. Effect of Active Droop on ESR The processor regulation window including transients is speciﬁed as +100mV..–50mV. To accommodate the droop, the output voltage of the converter is raised by about 30mV at no load. The converter response to the load step is shown in Figure 8. At zero load current, the output voltage is raised ~30mV above nominal value of 1.5V. When the load current increases, the output voltage droops down approximately 55mV. Due to use of Active Droop, the converter’s output voltage adaptively changes with the load current allowing better utilization of the regulation window. Figure 8. Converter response to 5A load step The current through each RSENSE resistor (ISNS) is sam- pled shortly after LDRV is turned on. That current is held for the remainder of the cycle, and then injected to produce an offset to VCORE+ through the external 1K resistor (R6 in Figure 1). This creates a voltage at the input to the error ampliﬁer that rises with increasing current, causing the regu- lator’s output to droop as the current increases. VDROOP = -I-L---O--3--A---•-D---R--•---S-R--E---D-N--S--S--(-E-O----N---) (7) Gate Driver section The gate control logic translates the internal PWM control signal into the MOSFET gate drive signals providing necessary ampliﬁcation, level shifting and shoot-through protection. Also, it has functions that help optimize the IC performance over a wide range of operating conditions. Since MOSFET switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to- source voltages of both upper and lower MOSFETs. The lower MOSFET drive is not turned on until the gate-to- source voltage of the upper MOSFET has decreased to less than approximately 1 volt. Similarly, the upper MOSFET is not turned on until the gate-to-source voltage of the lower MOSFET has decreased to less than approximately 1 volt. This allows a wide variety of upper and lower MOSFETs to be used without a concern for simultaneous conduction, or shoot-through. There must be a low – resistance, low – inductance path between the driver pin and the MOSFET gate for the adap- tive dead-time circuit to work properly. Any delay along that path will subtract from the delay generated by the adaptive dead-time circit and a shoot-through condition may occur. Frequency Loop Compensation Due to the implemented current mode control, the modulator has a single pole response with -1 slope at frequency deter- mined by load FPO = 2----π----R---1-O----C-----O-- (8) where RO is load resistance, CO is load capacitance. For this type of modulator Type 2 compensation circuit is usually sufﬁcient. To reduce the number of external components and simplify the design task, the PWM controller has an inter- nally compensated error ampliﬁer. Figure 9 shows a Type 2 ampliﬁer and its response along with the responses of a cur- rent mode modulator and of the converter. The Type 2 ampli- ﬁer, in addition to the pole at the origin, has a zero-pole pair that causes a ﬂat gain region at frequencies between the zero and the pole. REV. 1.1.7 8/29/02 11 11 Page

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