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PDF FAN5068 Data sheet ( Hoja de datos )
| Número de pieza | FAN5068 | |
| Descripción | DDR-1/DDR-2 plus ACPI Regulator Combo | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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FAN5068
DDR-1/DDR-2 plus ACPI Regulator Combo
Features
• PWM regulator for VDDQ (2.5V or 1.8V)
• Linear LDO regulator generates VTT = VDDQ/2, 1.5A
Peak sink/source capability
• 1 independent programable ULDO controllers driving
external N-Channel MOSFET
• ACPI drive and control for 5V DUAL generation
• 3.3V Internal LDO for 3V-ALW generation
• 300kHz fixed frequency switching
• RDS(ON) current sensing or optional current sense resistor
for precision over-current detect
• Internal Synchronous Boot diode
• Power Good signal for all voltages
• Input Under-Voltage Lock-Out (UVLO)
• Thermal Shutdown
• Latched Multi-Fault Protection
• 24-pin 5x5mm MLP package
Applications
• DDR-1/DDR-2 VDDQ and VTT voltage generation with
ACPI support
• Desktop PC's
• Servers
General Description
The FAN5068 DDR memory regulator combines a high-
efficiency PWM controller to generate the supply voltage,
VDDQ, and a linear regulator to generate VTT, the termina-
tion voltage. Synchronous rectification provides high-
efficiency over a wide range of load currents. Efficiency is
further enhanced by using the low-side MOSFET’s RDS(ON)
to sense current instead of a series sense resistor.
In S3 mode, only the VDDQ switcher and the 3.3V regula-
tors remain on while the VTT and ULDO regulators are shut
off. To avoid "glitching" the VDDQ output during the transi-
tion from S3 to S0, the three linear regulators use the SS
capacitor to limit their slew rates, thereby limiting the surge
current from the VDDQ output. PGOOD becomes true in S0
only when all 3 regulators have achieved stable outputs.
In S5 (EN = 0), the 3.3V internal LDO stays on, while the
other regulators are powered down.
The VDDQ PWM regulator is a sampled current mode con-
trol with external compensation to achieve fast load transient
response and provide system design optimization.
The VTT regulator derives its reference and takes its power
from the VDDQ PWM regulator output using a precision
internal voltage divider to set its output at 1/2 of VDDQ. The
VTT termination regulator is capable of sourcing or sinking
at least 1.5A peak current.
REV. 1.0.1 9/9/04
1 page  
FAN5068
PRODUCT SPECIFICATION
Pin Definitions (continued)
Pin # Pin Name
8 BOOT
9 HDRV
10 SW
11 ISNS
12 LDRV
13 PGOOD
14 VCC
15 3.3 ALW
16 S3#O
17 S3#I
18 EN
19 GND
20 ILIM
21 SS
22 COMP
23 FB
24 REF IN
Pin Function Description
Boot. Positive supply for the upper MOSFET driver. Connect as shown in Figure 1. IC
contains a boot diode to VCC.
High-Side Drive. High-side (upper) MOSFET driver output. Connect to gate of high-side
MOSFET.
Switching Node. Return for the high-side MOSFET driver and a current sense input.
Connect to source of high-side MOSFET and low-side MOSFET drain.
Current Sense Input. Monitors the voltage drop across the lower MOSFET or external
sense resistor for current feedback.
Low-Side Drive. The low-side (lower) MOSFET driver output. Connect to gate of low-side
MOSFET.
Power Good Flag. An open-drain output that will pull LOW when FB is outside of a ±10%
range of the 0.9V reference and the LDO outputs are > 80% or < 110% of its reference.
PGOOD goes low when S3 is high. The power good signal from the PWM regulator enables
the VTT regulator and the LDO controller.
VCC. The IC takes its bias power from this pin. Also used for gate drive power. The IC is held
in standby until this pin is above 4.35V (UVLO threshold).
3.3V LDO Output. Internal LDO output. Turned off in S0, on in S5 or S3 modes.
S3# Output. Open-drain output which pulls the gates of two N-Channel blocking MOSFETs
low in S5 and S3. This pin goes high (open) in S0 mode.
S3 Input. When LOW, turns off the VTT and 1.2V LDO regulators and turns on the 3.3V
regulator. Also causes S3#O to pull low to turn off blocking switch Q3 as shown in Figure 1.
PGOOD is low when S3#I is LOW.
ENABLE. Typically tied to S5#. When this pin is low, the IC is in a low quiescent current
state, all regulators are off and S3#O is low.
GROUND for the IC are tied to this pin and also connected to P1.
Current Limit. A resistor from this pin to GND sets the current limit.
Soft Start. A capacitor from this pin to GND programs the slew rate of the converter during
initialization as well as sets the initial slew rate of the LDO controllers when transitioning from
S3 to S0. This pin is charged/discharged with a 5µA current source during initialization, and
charged with 50µA during PWM soft-start.
Output of the PWM error amplifier. Connect compensation network between this pin and
FB.
VDDQ Feedback. The feedback from PWM output. Used for regulation as well as PGOOD,
under-voltage, and over-voltage protection and monitoring.
VTT Reference. Input which provides the reference for the VTT regulator. A precision
internal divider from VDDQ IN is provided.
REV. 1.0.1 9/9/04
5
5 Page 
FAN5068
COMP
FB
SS/EN
CSS
COMP
FB
SS
1µA
ISS
–
+ E/A
+
VREF
ISNS
RAMP
–
+ PWM
+
PRODUCT SPECIFICATION
Figure 7. SS Clamp and FB Open Protection
4.41K
Reference and
Soft Start
TO
PWM
COMP
S/H
V to I
ISNS
ISNS
in +
in –
ILIM det.
2.5V
I2 =
ILIM*9.6
0.9V
ILIM
mirror
RSENSE
ISNS
LDRV
PGND
ILIM
RILIM
Figure 8. Current Limit / Summing Circuits
Current Processing Section
The following discussion refers to Figure 8.
The current through RSENSE resistor (ISNS) is sampled
shortly after Q2 is turned on. That current is held, and
summed with the output of the error amplifier. This effec-
tively creates a current mode control loop. RSENSE sets the
gain in the current feedback loop. For stable operation, the
voltage induced by the current feedback at the PWM com-
parator input should be set to 30% of the ramp amplitude at
maximum load currrent and line voltage. The following
expression estimates the recommended value of RSENSE as a
function of the maximum load current (ILOAD(MAX)) and the
value of the MOSFET’s RDS(ON).:
RSENSE = I---L---O--3--A-0--D-%---(--M--•---A-0--X-.-1--)-2--•-5---R--•---D-V--S---I(--NO---(-N-M---)--A-•--X--4--)-.-1----k- – 100
(5)
RSENSE must, however, be kept higher than:
RSENSE(MIN) = -I--L---O----A---D----(--M---1--A-5--X-0---µ)---•-A---R-----D---S---(--O----N----) – 100
(6)
Setting the Current Limit
An ISNS is compared to the current established when a 0.9 V
internal reference drives the ILIM pin. RILIM, the RDS(ON) of
Q2, and RSENSE determine the current limit:
RILIM
=
-----9---.--6------
ILIMIT
×
-(--1---0---0----+-----R-----S---E---N---S---E----)
RDS(ON)
(7)
Where ILIMIT is the peak inductor current. Since the toler-
ance on the current limit is largely dependent on the ratio of
the external resistors it is fairly accurate if the voltage drop
on the Switching Node side of RSENSE is an accurate repre-
sentation of the load current. When using the MOSFET as
the sensing element, the variation of RDS(ON) causes propor-
tional variation in the ISNS. This value not only varies from
device to device, but also has a typical junction temperature
coefficient of about 0.4%/°C (consult the MOSFET datasheet
for actual values), so the actual current limit set point will
decrease propotional to increasing MOSFET die tempera-
ture. A factor of 1.6 in the current limit setpoint should
compensate for all MOSFET RDS(ON) variations, assuming
the MOSFET’s heat sinking will keep its operating die
temperature below 125°C.
REV. 1.0.1 9/9/04
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet FAN5068.PDF ] | |
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