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PDF F50N06LE Data sheet ( Hoja de datos )

Número de pieza F50N06LE
Descripción 50A/ 60V/ 0.022 Ohm/ Logic Level N-Channel Power MOSFETs
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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RFG50N06LE, RFP50N06LE, RF1S50N06LESM
Data Sheet
October 1999 File Number 4072.3
50A, 60V, 0.022 Ohm, Logic Level
N-Channel Power MOSFETs
These N-Channel enhancement mode power MOSFETs are
manufactured using the latest manufacturing process
technology. This process, which uses feature sizes
approaching those of LSI circuits, gives optimum utilization
of silicon, resulting in outstanding performance. They were
designed for use in applications such as switching
regulators, switching converters, motor drivers, and relay
drivers. These transistors can be operated directly from
integrated circuits.
Formerly developmental type TA49164.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFG50N06LE
TO-247
FG50N06L
RFP50N06LE
TO-220AB
FP50N06L
RF1S50N06LESM TO-263AB
F50N06LE
NOTE: When ordering, use the entire part number. Add the suffix 9A
to obtain the TO-263AB variant in tape and reel, i.e.
RF1S50N06LESM9A.
Packaging
JEDEC STYLE TO-247
DRAIN
(BOTTOM
SIDE METAL)
SOURCE
DRAIN
GATE
Features
• 50A, 60V
• rDS(ON) = 0.022
• Temperature Compensating PSPICE® Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
JEDEC TO-220AB
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
JEDEC TO-263AB
GATE
SOURCE
DRAIN
(FLANGE)
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999

1 page




F50N06LE pdf
RFG50N06LE, RFP50N06LE, RF1S50N06LESM
Typical Performance Curves Unless Otherwise Specified (Continued)
2.0
VGS = VDS, ID = 250µA
1.5
1.2
1.1
ID = 250µA
1.0 1.0
0.5 0.9
0
-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
2500
2000
1500
1000
500
0
0
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS CDS + CGD
CISS
COSS
CRSS
5 10 15 20
VDS, DRAIN TO SOURCE VOLTAGE (V)
25
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
VDS
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
L
DUT
+
VDD
-
IAS
0.01
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
5
0.8
-80
-40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
200
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
60
VDD = BVDSS
VDD = BVDSS
5.0
45
RL =1.2
IG(REF) = 1.2mA
VGS = 5V
30
PLATEAU VOLTAGES IN
DESCENDING ORDER:
3.75
2.5
VDD = BVDSS
15
VDD = 0.75 BVDSS
1.25
VDD = 0.50 BVDSS
VDD = 0.25 BVDSS
00
20 I-I-GG-----((--AR----CE----FT----)) t, TIME (µs) 80 I-I-GG-----((--AR----CE----FT----))
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
tP
IAS
BVDSS
VDS
VDD
0
tAV
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS

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