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PDF FDC6302P Data sheet ( Hoja de datos )
| Número de pieza | FDC6302P | |
| Descripción | Digital FET/ Dual P-Channel | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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October 1997
FDC6302P
Digital FET, Dual P-Channel
General Description
These Dual P-Channel logic level enhancement mode field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. This device
has been designed especially for low voltage applications as a
replacement for digital transistors in load switchimg applications.
Since bias resistors are not required this one P-Channel FET
can replace several digital transistors with different bias resistors
like the IMBxA series.
Features
-25 V, -0.12 A continuous, -0.5 A Peak.
RDS(ON) = 13 Ω @ VGS= -2.7 V
RDS(ON) = 10 Ω @ VGS = -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. VGS(th) < 1.5V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace multiple PNP digital transistors (IMHxA series) with
one DMOS FET.
SOT-23
SuperSOTTM-6
SuperSOTTM-8
SO-8
SOT-223
SOIC-16
Absolute Maximum Ratings TA = 25oC unless other wise noted
Symbol Parameter
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage
ID Drain Current
- Continuous
- Pulsed
PD Maximum Power Dissipation
(Note 1a)
(Note 1b)
TJ,TSTG
ESD
Operating and Storage Temperature Range
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a)
RθJC Thermal Resistance, Junction-to-Case (Note 1)
© 1997 Fairchild Semiconductor Corporation
4
5
6
FDC6302P
-25
-8
-0.12
-0.5
0.9
0.7
-55 to 150
6.0
140
60
3
2
1
Units
V
V
A
W
°C
kV
°C/W
°C/W
FDC6302P Rev.C
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet FDC6302P.PDF ] | |
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