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PDF FDC6301N Data sheet ( Hoja de datos )
| Número de pieza | FDC6301N | |
| Descripción | Dual N-Channel / Digital FET | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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July 1997
FDC6301N
Dual N-Channel , Digital FET
General Description
These dual N-Channel logic level enhancement mode field
effect transistors are produced using Fairchild 's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
This device has been designed especially for low voltage
applications as a replacement for digital transistors. Since bias
resistors are not required, these N-Channel FET's can replace
several digital transistors, with a variety of bias resistors.
Features
25 V, 0.22 A continuous, 0.5 A Peak.
RDS(ON) = 5 Ω @ VGS= 2.7 V
RDS(ON) = 4 Ω @ VGS= 4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. VGS(th) < 1.5V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model.
SOT-23
SuperSOTTM-6
Mark: .301
SuperSOTTM-8
4
5
6
SO-8
SOT-223
SOIC-16
3
2
IN
1
INVERTER APPLICATION
D
Vcc
OUT
GS
GND
Absolute Maximum Ratings TA = 25oC unless other wise noted
Symbol Parameter
VDSS, VCC
VGSS, VIN
ID, IOUT
Drain-Source Voltage, Power Supply Voltage
Gate-Source Voltage, VIN
Drain/Output Current - Continuous
- Pulsed
PD Maximum Power Dissipation
(Note 1a)
(Note 1b)
TJ,TSTG
ESD
Operating and Storage Temperature Range
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
THERMAL CHARACTERISTICS
RθJA
RθJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
© 1997 Fairchild Semiconductor Corporation
FDC6301N
25
8
0.22
0.5
0.9
0.7
-55 to 150
6.0
140
60
Units
V
V
A
W
°C
kV
°C/W
°C/W
FDC6301N Rev.C
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet FDC6301N.PDF ] | |
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