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PDF FDC37CXFR Data sheet ( Hoja de datos )
| Número de pieza | FDC37CXFR | |
| Descripción | Plug and Play Compatible Ultra I/O Controller with Fast IR | |
| Fabricantes | SMSC Corporation | |
| Logotipo |  |
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FDC37C93xFR
ADVANCE INFORMATION
Plug and Play Compatible Ultra I/O™ Controller
with Fast IR
FEATURES
• 5 Volt Operation
- Software and Register Compatible with
• ISA Plug-and-Play Standard (Version 1.0a)
SMSC's Proprietary 82077AA
Compatible Register Set
Compatible Core
• Soft Power Management, SMI Support
• ACCESS.bus Support
• 8042 Keyboard Controller
- 2K Program ROM
- 256 Bytes Data RAM
- Asynchronous Access to Two Data
Registers and One Status Register
- Supports Interrupt and Polling Access
- 8 Bit Timer/Counter
- Port 92 Support
- Fast Gate A20 and Hardware Keyboard
Reset
• Real Time Clock
- MC146818 and DS1287 Compatible
- 256 Bytes of Battery Backed CMOS in
Two Banks of 128 Bytes
- 128 Bytes of CMOS RAM Lockable in
4x32 Byte Blocks
- 12 and 24 Hour Time Format
- Binary and BCD Format
- 1µA Standby Current (typ)
• Intelligent Auto Power Management
• 2.88MB Super I/O Floppy Disk Controller
- Relocatable to 480 Different Addresses
- 13 IRQ Options
- Four DMA Options
- Licensed CMOS 765B Floppy Disk
Controller
- Sophisticated Power Control Circuitry
(PCC) Including Multiple Powerdown
Modes for Reduced Power Consumption
- Game Port Select Logic
- Supports Two Floppy Drives Directly
- 24mA AT Bus Drivers
- Low Power CMOS Design
• Licensed CMOS 765B Floppy Disk
Controller Core
- Supports Vertical Recording Format
- 16 Byte Data FIFO
- 100% IBM® Compatibility
- Detects All Overrun and Underrun
Conditions
- 48mA Drivers and Schmitt Trigger Inputs
- DMA Enable Logic
- Data Rate and Drive Control Registers
• Enhanced Digital Data Separator
- Low Cost Implementation
- No Filter Components Required
- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps,
250 Kbps Data Rates
- Programmable Precompensation Modes
• Serial Ports
- Relocatable to 480 Different Addresses
- 13 IRQ Options
- Two High Speed NS16C550 Compatible
UARTs with Send/Receive 16 Byte FIFOs
- Advanced Digital Data Separator
1 page  
DESCRIPTION OF PIN FUNCTIONS
PIN NO.
NAME
SYMBOL
PROCESSOR/HOST INTERFACE
72:79 System Data Bus
SD[0:7]
41:52 System Address Bus
SA[0:11]
53 Chip Select/SA12 (Active Low)(Note 1, 4)
nCS
70 Address Enable (DMA master has bus control)
AEN
90 I/O Channel Ready
IOCHRDY
80
67:61,
59:54
82,84,
86,88
Reset Drive
Interrupt Requests [1,3:12,14,15]
(Polarity control for IRQ8)
DMA Requests
RESET_DRV
IRQ[1,3:12,
14,15]
DRQ[0:3]
81,83, DMA Acknowledge
85,87
nDACK[0:3]
89 Terminal Count
TC
68 I/O Read
nIOR
69 I/O Write
nIOW
35 High Speed Clock Out 24/48 MHz
HCLK
36 16 MHz Out
16CLK
22 14.318 MHz Clock Input
CLOCKI
37 14.318 MHz Clock Output 1
CLKO1
38 14.318 MHz Clock Output 2
CLKO2
39 14.318 MHz Clock Output 3
CLKO3
POWER PINS
21, 60, +5V Supply Voltage
101, 125,
139
VCC
32 Trickle Voltage Input
VTR
1, 8, 40, Ground
71, 95,
123, 130
GND
FDD INTERFACE
17 Read Disk Data
nRDATA
12 Write Gate
nWGATE
BUFFER TYPE
I/O24
I
I
I
OD24
IS
024/OD24
(Note 0)
O24
I
I
I
I
O20
O8SR
ICLK
O16SR
O8SR
O8SR
IS
OD48
5
5 Page 
Pin Original Alternate Alternate Alternate Buffer
No. Function Function 1 Function 2 Function 3 Type
108 GPI/O
Serial
EEPROM
-
- I/O4
Clock
109 GPI/O
Serial
EEPROM
-
- I/O4
Enable
110 GPI/O 8042 P21
-
- I/O4
Default
input
input
input
Index
Register
GP2
GPI/O
GP23
GP2 GP24
GP2 GP25
Note 1: At power-up, RD0-RD7, nROMCS and nROMOE function as the XD Bus. To use RD0-RD7
for functions other than the XD Bus, nROMCS must stay high until those pins are finished
being reprogrammed.
Note 2: These pins are input (high-z) until programmed for second serial port.
Note 3: This is the trickle voltage input pin for the FDC37C93xFR.
Note 4: These pins cannot be programmed as open drain pins in their original function.
Note 5: No pins in their original function can be programmed as inverted input or inverted output.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet FDC37CXFR.PDF ] | |
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