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PDF FC106 Data sheet ( Hoja de datos )

Número de pieza FC106
Descripción Fibre Channel Transceiver 1.0625 GBaud
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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No Preview Available ! FC106 Hoja de datos, Descripción, Manual

® FC106
Fibre Channel Transceiver 1.0625 GBaud
FEATURES
s Serial Link Transceiver
q serializer and deserializer
q implementing the Fibre Channel FC0
and FC1 layers
s Direct support for 1.0625 GBaud Fibre
Channel (ANSI X3.230-1994) rates
s Fibre Channel 10-bit Interface (ANSI
TR/X3.18-199X)
s Direct interfaces to optical tranceivers
s Plesiochronous mode operation
q transmitter and receiver clock
frequencies may differ by up to 100 ppm
s Integrated Fibre Channel 8b/10b
encode/decode (optional use through
JTAG)
s Byte and word synchronization of
incoming serial stream
s Supports any DC-balanced encoding
scheme
s Internal Loop-Back for Self-Test
s Random Pattern Auto-Test
s Optional integrated impedance
adaptation to transmission line
characteristics (50 or 75 ohms)
s TTL compatible parallel I/O’s
s JTAG Test Access Port
s 0.35µ CMOS Technology for low cost
and low power
s PQFP package available in two sizes:
14x14 mm (FC106/14) or 10x10 mm
(FC106/10)
PRELIMINARY DATA
Receive
Byte
Clock
Parallel Interface
REFCLK
10 bits
8 bit / 10 bit
DECODER
(optional)
8 bit / 10 bit
ENCODER
(optional)
DESER IALIZER
CLOCK RECOVERY
BYTE AND WORD
ALIGNEMENT
SERIALI ZER
AND CLOCK
FREQ UENCY
MULTIPLIC ATION
FC 106
1.0625 Gbaud
Serial data over copper
or optical cables
APPLICATIONS
s Fibre Channel Arbitrated Loop
s Fibre Channel fabric
s Transmission schemes encoding
bytes as 10-bit characters to form a
DC-balanced stream
s High performance backplane
interconnect
1/32
September 98
Revision 1.2

1 page




FC106 pdf
FC106
The FC106 integrates a loop-back path for system-level test purposes. It also includes a
self-test capability in which random patterns are transmitted through the internal loop-back
path and compared after reception.
The FC106 is implemented in a standard digital 0.35µ CMOS process. Its typical power
consumption is 0.4 Watts (not including the power required to drive the TTL parallel output
port, which is in the 0.1 Watt range for output capacitive loads of 10 pF per pin).
5/32
September 98
Revision 1.2

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FC106 arduino
FC106
example, if the REFCLK used is 106.25 MHz, then the incoming data serial signaling rate
must be 1.0625 ± 0.0001 Gb/s.
The FC106 provides 2 TTL recovered clocks RBC[0] and RBC[1], which are both driven at a
frequency of one twentieth of the serial signaling rate. These clocks are generated by the
clock recovery DLL, which is phase locked to the serial data. RBC[1] is 180° out of phase
with RBC[0]. If serial data is not present, or does not meet the required transition density or
signaling rate, the RBC frequencies will be half of the expected recovered clock frequency
(defined by REFCLK). This function replaces the optional LCK_REF signal that is specified
in the Fibre Channel 10-bit interface. When no data is present, phase adjustments are
required for switching between a locking to incoming data and locking to REFCLK. The
specification on output clocks RBC[0:1] is maintained during these adjustments.The clock
periods are not truncated.
The serial data is retimed and deserialized. Parallel data is loaded into the output register,
and therefore accessible on the output data port. For Fibre Channel use, bytes 1 and 3 of the
receive data word will be accessible on the rising edge of RBC[0], and bytes 0 and 2 on the
rising edge of RBC[1].
Word synchronization is enabled in the FC106 by connecting the EN_CDET pin to Vdd.
When EN_CDET is set high, the FC106 examines serial data for the presence of a positive
disparity comma symbol (0011111). Improper alignment occurs when a comma symbol
straddles a 10-bit boundary or is not aligned within the 10-bit transmission character. Proper
alignment is reached by shifting the boundary of the parallel output.
At power up the FC106 will not be in synchronization and data alignment is not established.
The COM_DET output signal is then set low. When a comma symbol is detected, COM_DET
is set high (if EN_CDET is already set high). COM_DET will go high only during a cycle in
which RBC[1] is rising (see Section 6.2.2: Receive interface timing on page 23 for precise
timing).
Note that if EN_CDET is set low, but a comma is detected while the input stream is already
word-aligned, COM_DET will be set high again.
3.9 Bit alignment
The alignment block aligns the incoming data bit stream and the reference clocks generated
by the DLL Clock Generator. It compensates for clock frequency dispersions between the
crystals generating the respective reference clocks REFCLK of the transmitting and
receiving chips.
11/32
September 98
Revision 1.2

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