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PDF FBL2031 Data sheet ( Hoja de datos )
| Número de pieza | FBL2031 | |
| Descripción | 9-bit BTL 3.3V latched/registered/pass-thru Futurebus transceiver | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
FBL2031
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
Product specification
Supersedes data of 1998 Sep 04
2000 Apr 18
Philips
Semiconductors
1 page  
Philips Semiconductors
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
Product specification
FBL2031
FUNCTION TABLE
MODE
An to Bn thru mode
An to Bn transparent latch
An to Bn latch and read
Bn outputs latched and read
(preconditioned latch)
An to Bn register
Bn to An thru mode
Bn to An transparent latch
Bn to An latch and read
An outputs latched and read
(preconditioned latch)
Bn to An register
Disable Bn outputs
Disable An outputs
INPUTS
OUTPUTS
An Bn* OEB0 OEB1 OEA LCAB LCBA SEL0 SEL1 An
Bn
L —H L L X X H
L input H**
H—H L L X X H
L input L
L — H L L L X L L input H**
H—H
L
L
L
X
L
L input L
l — H L L ↑ X L L input H**
h — H L L ↑ X L L input L
X—H L X H X
L
L
X
latched
data
l — H L L ↑ X X H input H**
h — H L L ↑ X X H input L
—L
Disable
H X X H L H input
—H
Disable
HXX H
L
L input
—L
Disable
H X L L L H input
— H Disable H X L L L L input
—L
Disable
H X L H H H input
—H
Disable
H X L H H L input
—l
Disable
HX ↑ L
L H input
—h
Disable
HX ↑ L L
L input
—l
Disable
H X ↑ H H H input
—h
Disable
H X ↑ H H L input
—X X X H X H L
L
latched
data
X
—X X X H X H H
H
latched
data
X
—l
Disable
H X ↑ L H H input
—h
Disable
H X ↑ L H L input
X X L X X X X X X X H**
X X X H X X X X X X H**
XXXXL X X X X Z X
FUNCTION SELECT TABLE
MODE SELECTED
Thru mode
Register mode (An to Bn)
Latch mode (An to Bn)
Register mode (Bn to An)
Latch mode (Bn to An)
NOTES:
H = High voltage level
L = Low voltage level
l = Low voltage level one set-up time prior to the Low-to-High
LCXX transition
h = High voltage level one set-up time prior to the Low-to-High
LCXX transition
X = Don’t care
SEL0
H
X
L
L
L
H
SEL1
L
H
L
H
L
H
Z = High-impedance (OFF) state
— = Input not externally driven
↑ = Low-to-High transition
H** = Goes to level of pull-up voltage
Bn* = Precaution should be taken to ensure B inputs do not float.
If they do, they are equal to Low state.
Disable = OEB0 is Low or OEB1 is High.
2000 Apr 18
5
5 Page 
Philips Semiconductors
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
Product specification
FBL2031
AC ELECTRICAL CHARACTERISTICS
A TO B 16.5 Ω LOAD SPECIFICATIONS
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = +25°C,
VCC = 3.3V,
MIN TYP MAX
Tamb = –40 to +85°C,
VCC = 3.3V±10%,
MIN MAX
UNIT
tPLH Propagation delay (thru latch)
tPHL
An to Bn
Waveform 1, 2
1.4 2.7 3.9
1.2 2.4 3.6
1.0
1.0
5.0
4.0
ns
tPLH Propagation delay (transparent latch)
tPHL
An to Bn
Waveform 1, 2
1.8 3.0 4.2
2.0 3.2 4.7
1.0
1.4
5.6
5.5
ns
tPLH Propagation delay
tPHL LCAB to Bn (latch)
Waveform 1, 2
8.6 11.4 14.2
8.0 10.6 13.3
6.5
6.4
17.5
16.1
ns
tPLH Propagation delay
tPHL LCAB to Bn (register)
Waveform 1, 2
2.2 3.5 4.8
2.3 3.7 5.1
1.2
1.7
6.1
5.9
ns
tPLH Propagation delay
tPHL SEL0 or SEL1 to Bn (inverting)
Waveform 1, 2
2.6 4.5 6.7
1.4 4.4 7.7
1.5
1.1
8.1
8.4
ns
tPLH Propagation delay
tPHL SEL0 or SEL1 to Bn (non-inverting)
Waveform 1, 2
2.2 4.5 6.9
2.3 4.0 5.8
1.4
1.5
8.2
6.9
ns
tPLH
tPHL
OEB0 to Bn
Waveform 1, 2
1.8 3.1 4.4
1.7 2.9 4.2
1.0
1.0
5.8
6.0
ns
tTLH Output transition time, Bn Port
tTHL (1.3V to 1.8V)
Test Circuit and
Waveforms
1.2
0.4
3.0
1.5
ns
tSK(o)
Output to output skew for multiple
channels1
Waveform 3
0.5 1.0
2.0 ns
tSK(p)
Pulse skew2
tPHL – tPLH MAX
Waveform 2
0.5 1.0
1.5 ns
NOTES:
1. tPNactual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or
HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). tSK (0) compares tPLH on a given path to tPLH
on any other path or compares tPHL on a given path to tPHL on any other path.
2. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal
duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).
2000 Apr 18
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet FBL2031.PDF ] | |
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