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PDF FM27C512QE150 Data sheet ( Hoja de datos )

Número de pieza FM27C512QE150
Descripción 524/288-Bit (64K x 8) High Performance CMOS EPROM
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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January 2000
FM27C512
524,288-Bit (64K x 8) High Performance CMOS EPROM
General Description
The FM27C512 is a high performance 512K UV Erasable Electri-
cally Programmable Read Only Memory (EPROM). It is manufac-
tured using Fairchild’s proprietary CMOS AMG™ EPROM tech-
nology for an excellent combination of speed and economy while
providing excellent reliability.
The FM27C512 provides microprocessor-based systems storage
capacity for portions of operating system and application soft-
ware. Its 90 ns access time provides no wait-state operation with
high-performance CPUs. The FM27C512 offers a single chip
solution for the code storage requirements of 100% firmware-
based equipment. Frequently-used software routines are quickly
executed from EPROM storage, greatly enhancing system utility.
The FM27C512 is configured in the standard JEDEC EPROM
pinout which provides an easy upgrade path for systems which are
currently using standard EPROMs.
The FM27C512 is one member of a high density EPROM Family
which range in densities up to 4 Megabit.
Features
I High performance CMOS
— 90 ns access time
I Fast turn-off for microprocessor compatibility
I Manufacturers identification code
I JEDEC standard pin configuration
— 28-pin PDIP package
— 32-pin chip carrier
— 28-pin CERDIP package
Block Diagram
VCC
GND
VPP
OE
CE/PGM
Output Enable and
Chip Enable Logic
Data Outputs O0 - O7
Output
Buffers
Y Decoder
A0 - A15
Address
Inputs
X Decoder
524,288-Bit
Cell Matrix
AMG is a trademark of WSI, Inc.
© 1998 Fairchild Semiconductor Corporation
FM27C512
1
DS800035-1
www.fairchildsemi.com

1 page




FM27C512QE150 pdf
Programming Characteristics (Note 10) and (Note 11)
Symbol
tAS
tOES
tDS
tVCS
tAH
tDH
tCF
tPW
tOEH
tDV
tPRT
tVR
IPP
ICC
TR
VCC
VPP
tFR
VIL
VIH
tIN
tOUT
Parameter
Address Setup Time
OE Setup Time
Data Setup Time
VCC Setup Time
Address Hold Time
Data Hold Time
Chip Enable to Output Float Delay
Program Pulse Width
OE Hold Time
Data Valid from CE
OE Pulse Rise Time
during Programming
VPP Recovery Time
VPP Supply Current during
Programming Pulse
VCC Supply Current
Temperature Ambient
Power Supply Voltage
Programming Supply Voltage
Input Rise, Fall Time
Input Low Voltage
Input High Voltage
Input Timing Reference Voltage
Output Timing Reference Voltage
Conditions
OE = VIL
OE = VIL
CE = VIL
OE = VPP
Min
1
1
1
1
0
1
0
45
1
50
1
20
6.25
12.5
5
2.4
0.8
0.8
Typ
50
25
6.5
12.75
0
4
Max
60
105
250
30
50
30
6.75
13
0.45
2
2
Units
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
µs
mA
mA
°C
V
V
ns
V
V
V
V
Programming Waveforms
Addresses
2.0V
0.8V
Data
2.0V
0.8V
OE/VPP
12.75V
0.8V
CE/PGM
tPRT
Program
Address N
t AS
Data In Stable
ADD N
t DS t DH
Hi-Z
t OES
t VPS
t VCS
t PW
t OEH
t VR
Program Verify
2.0V
0.8V
t DV
Data Out Valid
ADD N
t CF
t AH
VCC 6.25V
DS800035-5
Note 10: Fairchilds standard product warranty applies to devices programmed to specifications described herein.
Note 11: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with
voltage applied to VPP or VCC.
Note 12: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VCC to GND to suppress spurious voltage transients which
may damage the device.
FM27C512
5 www.fairchildsemi.com

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