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PDF FM27C256NE150 Data sheet ( Hoja de datos )

Número de pieza FM27C256NE150
Descripción 262/144-Bit (32K x 8) High Performance CMOS EPROM
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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January 2000
FM27C256
262,144-Bit (32K x 8) High Performance CMOS EPROM
General Description
The FM27C256 is a 256K Electrically Programmable Read Only
Memory. It is manufactured in Fairchild’s latest CMOS split gate
EPROM technology which enables it to operate at speeds as fast
as 90 ns access time over the full operating range.
The FM27C256 provides microprocessor-based systems exten-
sive storage capacity for large portions of operating system and
application software. Its 90 ns access time provides high speed
operation with high-performance CPUs. The FM27C256 offers a
single chip solution for the code storage requirements of 100%
firmware-based equipment. Frequently-used software routines
are quickly executed from EPROM storage, greatly enhancing
system utility.
The FM27C256 is configured in the standard EPROM pinout
which provides an easy upgrade path for systems which are
currently using standard EPROMs.
The FM27C256 is one member of a high density EPROM Family
which range in densities up to 4 Mb.
Features
I High performance CMOS
— 90 ns access time
I JEDEC standard pin configuration
— 28-pin PDIP package
— 32-pin chip carrier
— 28-pin CERDIP package
I Drop-in replacement for 27C256 or 27256
I Manufacturer’s identification code
Block Diagram
VCC
GND
VPP
OE
CE/PGM
Output Enable
and Chip Enable Logic
Data Outputs O0 - O7
Output
Buffers
Y Decoder
A0 - A14
Address
Inputs
X Decoder
Y Gating
© 1998 Fairchild Semiconductor Corporation
FM27C256
1
DS800034-1
www.fairchildsemi.com

1 page




FM27C256NE150 pdf
Programming Characteristics (Note 12) (Note 13) (Note 14) (Note 15)
Symbol
tAS
tOES
tVPS
tVCS
tDS
tAH
tDH
tDF
tPW
tOE
IPP
ICC
TA
VCC
VPP
tFR
VIL
VIH
tIN
tOUT
Parameter
Address Setup Time
OE Setup Time
VPP Setup Time
VCC Setup Time
Data Setup Time
Address Hold Time
Data Hold Time
Output Enable to Output
Float Delay
Program Pulse Width
Data Valid from OE
VPP Supply Current
during Programming Pulse
VCC Supply Current
Temperature Ambient
Power Supply Voltage
Programming Supply Voltage
Input Rise, Fall Time
Input Low Voltage
Input High Voltage
Input Timing Reference Voltage
Output Timing Reference Voltage
Conditions
CE = VIL
CE = VIL
CE = VIL
Min
1
1
1
1
1
0
1
0
45
Typ
50
20 25
6.25 6.5
12.5 12.75
5
0.0
2.4 4.0
0.8
0.8
Programming Waveforms (Note 14)
PROGRAM
ADDRESSES 2.0V
0.8V
2.0V
DATA 0.8V
VCC 5.25V
ADDRESS N
tAS
DATA IN STABLE
ADD N
tDS tDH
tVCS
PROGRAM
VERIFY
tAH
DATA OUT VALID
ADD N
tDF
Max
60
105
100
30
50
30
6.75
13.0
0.45
2.0
2.0
Units
µs
µs
µs
µs
µs
µs
µs
ns
µs
ns
mA
mA
°C
V
V
ns
V
V
V
V
VPP 12.75V
tVPS
2.0V
CE 0.8V
2.0V
OE 0.8V
tOES
tOE
tPW
DS800034-5
Note 12: Fairchilds standard product warranty applies to devices programmed to specifications described herein.
Note 13: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with
voltage applied to VPP or VCC.
Note 14: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VPP, VCC to GND to suppress spurious voltage transients
which may damage the device.
Note 15: During power up the PGM pin must be brought high (VIH) either coincident with or before power is applied to VPP.
FM27C256
5 www.fairchildsemi.com

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