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PDF FM27C040QE120 Data sheet ( Hoja de datos )

Número de pieza FM27C040QE120
Descripción 4/194/304-Bit 512K x 8 High Performance CMOS EPROM
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FM27C040QE120 Hoja de datos, Descripción, Manual

January 2000
FM27C040
4,194,304-Bit (512K x 8) High Performance
CMOS EPROM
General Description
The FM27C040 is a high performance, 4,194,304-bit Electrically
Programmable UV Erasable Read Only Memory. It is organized
as 512K words of 8 bits each. Its pin-compatibility with byte-wide
JEDEC EPROMs enables upgrades through 8 Mbit EPROMs.
The “Don’t Care” feature on VPP during read operations allows
memory expansions from 1M to 8 Mbits with no printed circuit
board changes.
The FM27C040 provides microprocessor-based systems exten-
sive storage capacity for large portions of operating system and
application software. Its 120ns access time provides high speed
operation with high-performance CPUs. The FM27C040 offers a
single chip solution for the code storage requirements of 100%
firmware-based equipment. Frequently used software routines
are quickly executed from EPROM storage, greatly enhancing
system utility.
The FM27C040 is manufactured using Fairchild’s advanced CMOS
AMG™ EPROM technology.
Block Diagram
VCC
GND
VPP
OE
CE/PGM
Output Enable,
Chip Enable, and
Program Logic
Features
I High performance CMOS
— 120, 150ns access time*
I Simplified upgrade path
—VPP is a “Don’t Care” during normal read operation
I Manufacturer’s identification code
I JEDEC standard pin configuration
— 32-pin PDIP
— 32-pin PLCC
— 32-pin CERDIP
*Note: New revision meets 70ns. Please check with factory for availability.
Data Outputs O0 - O7
Output
Buffers
Y Decoder
Y Gating
A0 - A18
Address
Inputs
X Decoder
4,194,304-Bit
Cell Matrix
AMG™ is a trademark of WSI, Inc.
© 1999 Fairchild Semiconductor Corporation
FM27C040 Rev. A
1
DS800033-1
www.fairchildsemi.com

1 page




FM27C040QE120 pdf
Programming Waveform (Note 13)
ADDRESSES
2V
0.8V
2V
DATA
0.8V
6.25V
VPP
12.75V
VCC
Program
Address N
tAS
Data In Stable
ADD N
Hi-Z
tDS tDH
tVCS
tVPS
Program
Verify
tAH
Data Out Valid
ADD N
tDF
CE/PGM 2V
0.8V
OE 2V
0.8V
tPW
tOES
tOE
DS800033-5
Programming Characteristics (Notes 11, 12, 13, 14)
Symbol
tAS
tOES
tDS
tVPS
tVCS
tAH
tDH
tDF
tPW
tOE
IPP
ICC
TA
VCC
VPP
tFR
VIL
VIH
tIN
tOUT
Parameter
Address Setup Time
OE Setup Time
Data Setup Time
VPP Setup Time
VCC Setup Time
Address Hold Time
Data Hold Time
Output Enable to Output Float Delay
Program Pulse Width
Data Valid from OE
VPP Supply Current during
Programming Pulse
VCC Supply Current
Temperature Ambient
Power Supply Voltage
Programming Supply Voltage
Input Rise, Fall Time
Input Low Voltage
Input High Voltage
Input Timing Reference Voltage
Output Timing Reference Voltage
Conditions
CE/PGM = X
CE/PGM = X
CE/PGM = VIL
Min
1
1
1
1
1
0
1
0
45
20
6.25
12.5
5
-0.1
2.4
0.8
0.8
Typ
50
25
6.5
12.75
0.0
4.0
Max
60
105
100
30
30
30
6.75
13.0
0.45
2.0
2.0
Units
µs
µs
µs
µs
µs
µs
µs
ns
µs
ns
mA
mA
°C
V
V
ns
V
V
V
V
Note 11: Fairchilds standard product warranty applies only to devices programmed to specifications described herein.
Note 12: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with
voltage applied to VPP or VCC.
Note 13: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VPP, VCC to GND to suppress spurious voltage transients
which may damage the device.
Note 14: During power up the CE/PGM pin must be brought high (VIH) either coincident with or before power is applied to VPP.
FM27C040 Rev. A
5 www.fairchildsemi.com

5 Page





FM27C040QE120 arduino
Physical Dimensions inches (millimeters) unless otherwise noted
1.64 1.66
(41.66 42.164)
32
17
0.062 TYP
(1.575)
RAD
0.490 0.550
(12.446 13.97)
1
Pin No. 1 IDENT
16
0.580
(14.73)
MIN
0.600 0.620
(15.240 15.748)
0.050
(1.270)
TYP
90°105°
0.008 - 0.015
(0.203 0.381)
0.040 - 0.090
(1.016 2.286)
0.100 ±0.010
(2.540 ±0.254)
0.018 ±0.003
(0.457 ±0.078)
0.035 0.07
(0.889 1.778)
32-Lead PDIP Package
Order Number FM27C040NXXX
0.125 0.165
(3.175 4.191)
86°- 94°
TYP
0.145 0.210
(3.683 5.334)
0.015
(0.381)
0.120 0.150
(3.048 3.81)
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably ex-
pected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Americas
Customer Response Center
Tel. 1-888-522-5372
Fairchild Semiconductor
Europe
Fax: +44 (0) 1793-856858
Deutsch Tel: +49 (0) 8141-6102-0
English Tel: +44 (0) 1793-856856
Français Tel: +33 (0) 1-6930-3696
Italiano Tel: +39 (0) 2-249111-1
Fairchild Semiconductor
Hong Kong
8/F, Room 808, Empire Centre
68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
Fairchild Semiconductor
Japan Ltd.
4F, Natsume Bldg.
2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
FM27C040 Rev. A
11 www.fairchildsemi.com

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