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PDF FM27C010N120 Data sheet ( Hoja de datos )

Número de pieza FM27C010N120
Descripción 1/048/576-Bit 128K x 8 High Performance CMOS EPROM
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FM27C010N120 Hoja de datos, Descripción, Manual

January 2000
FM27C010
1,048,576-Bit (128K x 8) High Performance
CMOS EPROM
General Description
The FM27C010 is a high performance, 1,048,576-bit Electrically
Programmable UV Erasable Read Only Memory. It is organized
as 128K-words of 8 bits each. Its pin-compatibility with byte-wide
JEDEC EPROMs enables upgrades through 8 Mbit EPROMs.
The “Don’t Care” feature during read operations allows memory
expansions from 1M to 8M bits with no printed circuit board
changes.
The FM27C010 can directly replace lower density 28-pin EPROMs
by adding an A16 address line and VCC jumper. During the normal
read operation PGM and VPP are in a “Don’t Care” state which
allows higher order addresses, such as A17, A18, and A19 to be
connected without affecting the normal read operation. This
allows memory upgrades to 8M bits without hardware changes.
The FM27C010 is also offered in a 32-pin plastic DIP with the
same upgrade path.
The FM27C010 provides microprocessor-based systems exten-
sive storage capacity for large portions of operating system and
application software. Its 70 ns access time provides no-wait-state
operation with high-performance CPUs. The FM27C010 offers a
single chip solution for the code storage requirements of 100%
firmware-based equipment. Frequently-used software routines
are quickly executed from EPROM storage, greatly enhancing
system utility.
The FM27C010 is manufactured using Fairchild’s advanced CMOS
AMG™ EPROM technology.
The FM27C010 is one member of a high density EPROM Family
which range in densities up to 4 Megabit.
Features
I High performance CMOS
— 70 ns access time
I Fast turn-off for microprocessor compatibility
I Simplified upgrade path
— VPP and PGM are “Don’t Care” during normal read
operation
I Manufacturers identification code
I Fast programming
I JEDEC standard pin configurations
— 32-pin PDIP package
— 32-pin PLCC package
— 32-pin CERDIP package
Block Diagram
VCC
GND
VPP
OE
CE
PGM
Output Enable,
Chip Enable, and
Program Logic
Data Outputs O0 - O7
Output
Buffers
Y Decoder
A0 - A16
Address
Inputs
X Decoder
1,048,576-Bit
Cell Matrix
© 2000 Fairchild Semiconductor Corporation
FM27C010
1
DS800032-1
www.fairchildsemi.com

1 page




FM27C010N120 pdf
Programming Characteristics (Note 11), (Note 12), (Note 13), and (Note 14) (Continued)
Symbol
tOE
IPP
ICC
TA
VCC
VPP
tFR
VIL
VIH
tIN
tOUT
Parameter
Data Valid from OE
VPP Supply Current during
Programming Pulse
VCC Supply Current
Temperature Ambient
Power Supply Voltage
Programming Supply Voltage
Input Rise, Fall Time
Input Low Voltage
Input High Voltage
Input Timing Reference Voltage
Output Timing Reference Voltage
Conditions
CE = VIL
CE = VIL
PGM = VIL
Min Typ Max Units
100 ns
15 mA
20
20 25 30
6.2 6.5 6.75
12.5 12.75 13.0
5
0.0 0.45
2.4 4.0
0.8 2.0
0.8 2.0
mA
°C
V
V
ns
V
V
V
V
Programming Waveforms (Note 13)
Note 11: Fairchilds standard product warranty applies only to devices programmed to specifications describedPhroergerina.m
Program
Verify
ADDRESS
2V
0.8V
2V
DATA
0.8V
Address N
tAS
Data In Stable
ADD N
tDS tDH
Hi-Z
tAH
Data Out Valid
ADD N
tDF
6.25V
VCC
12.75V
VPP
tVCS
tVPS
CE
0.8V
PGM 2V
0.8V
OE 2V
0.8V
tCES
tPW
tOES
tOE
DS800032-5
Note 12: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with
voltage applied to VPP or VCC.
Note 13: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VPP, VCC to GND to suppress spurious voltage transients
which may damage the device.
Note 14: During power up the PGM pin must be brought high (VIH) either coincident with or before power is applied to VPP.
FM27C010
5 www.fairchildsemi.com

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