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Número de pieza | FM25CL04 | |
Descripción | 4Kb FRAM Serial 3V Memory | |
Fabricantes | ETC | |
Logotipo | ||
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FM25CL04
4Kb FRAM Serial 3V Memory
Features
4K bit Ferroelectric Nonvolatile RAM
• Organized as 512 x 8 bits
• Unlimited Read/Write Cycles
• 10 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
Very Fast Serial Peripheral Interface - SPI
• Up to 20 MHz Frequency
• Direct Hardware Replacement for EEPROM
• SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
Description
The FM25CL04 is a 4-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 10 years
while eliminating the complexities, overhead, and
system level reliability problems caused by
EEPROM and other nonvolatile memories.
Unlike serial EEPROMs, the FM25CL04 performs
write operations at bus speed. No write delays are
incurred. The next bus cycle may commence
immediately without the need for data polling. The
next bus cycle may start immediately. In addition, the
product offers virtually unlimited write endurance.
Also, FRAM exhibits much lower power
consumption than EEPROM.
These capabilities make the FM25CL04 ideal for
nonvolatile memory applications requiring frequent
or rapid writes or low power operation. Examples
range from data collection, where the number of
write cycles may be critical, to demanding industrial
controls where the long write time of EEPROM can
cause data loss.
The FM25CL04 provides substantial benefits to users
of serial EEPROM as a hardware drop-in
replacement. The FM25CL04 uses the high-speed
SPI bus, which enhances the high-speed write
capability of FRAM technology. Device
specifications are guaranteed over an industrial
temperature range of -40°C to +85°C.
Write Protection Scheme
• Hardware Protection
• Software Protection
Low Power Consumption
• Low Voltage Operation 2.7-3.65V
• 1 µA Standby Current
Industry Standard Configuration
• Industrial Temperature -40°C to +85°C
• 8-pin SOIC
Pin Configuration
CS
SO
WP
VSS
1
2
3
4
8 VDD
7 HOLD
6 SCK
5 SI
Pin Name
/CS
/WP
/HOLD
SCK
SI
SO
VDD
VSS
Function
Chip Select
Write Protect
Hold
Serial Clock
Serial Data Input
Serial Data Output
Supply Voltage
Ground
Ordering Information
FM25CL04-S 8-pin SOIC
This is a product in sampling or pre-production phase of develop-
ment. Characteristic data and other specifications are subject to
change without notice.
Rev. 1.0
July 2003
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
www.ramtron.com
Page 1 of 11
1 page Data Transfer
All data transfers to and from the FM25CL04 occur
in 8-bit groups. They are synchronized to the clock
signal (SCK), and they transfer most significant bit
(MSB) first. Serial inputs are registered on the rising
edge of SCK. Outputs are driven from the falling
edge of SCK.
Command Structure
There are six commands called op-codes that can be
issued by the bus master to the FM25CL04. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, there are
commands that have no subsequent operations. They
perform a single function such as to enable a write
operation. Second are commands followed by one
byte, either in or out. They operate on the status
register. The third group includes commands for
memory transactions followed by address and one or
more bytes of data.
Table 1. Op-code Commands
Name Description
WREN Set Write Enable Latch
WRDI Write Disable
RDSR Read Status Register
WRSR Write Status Register
READ Read Memory Data
WRITE Write Memory Data
Op-code
00000110b
00000100b
00000101b
00000001b
0000A011b
0000A010b
FM25CL04
WREN - Set Write Enable Latch
The FM25CL04 will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for
write operations. These include writing the status
register and writing the memory.
Sending the WREN op-code causes the internal
Write Enable Latch to be set. A flag bit in the status
register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the status
register has no effect. Completing any write
operation will automatically clear the write-enable
latch and prevent further writes without another
WREN command. Figure 5 below illustrates the
WREN command bus configuration.
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the status register and verifying that WEL=0. Figure
6 illustrates the WRDI command bus configuration.
CS
SCK
SI
SO
CS
SCK
Rev. 1.0
July 2003
SI
SO
01 2 3 4 5 6 7
00 00 0 11
Hi-Z
Figure 5. WREN Bus Configuration
0
01 2 3 4 5 6 7
00 00 0 10
Hi-Z
Figure 6. WRDI Bus Configuration
0
Page 5 of 11
5 Page 8-pin SOIC (JEDEC MS-012 variation AA)
FM25CL04
Index
Area
EH
Pin 1
D
B
e
A
A1
h
.10 mm
.004 in.
α
45 °
L
C
Selected Dimensions
Refer to JEDEC MS-012 for complete dimensions and notes.
Controlling dimensions in millimeters.
Conversions to inches are not exact.
Symbol Dim Min Nom. Max
A mm 1.35
1.75
in. 0.053
0.069
A1 mm 0.10
0.25
in. 0.004
0.010
B mm 0.33
0.51
in. 0.013
0.020
C mm 0.19
0.25
in. 0.007
0.010
D mm 4.80
5.00
in. 0.189
0.197
E mm 3.80
4.00
in. 0.150
0.157
e mm
1.27 BSC
in. 0.050 BSC
H mm 5.80
6.20
in. 0.228
0.244
h mm 0.25
0.50
in. 0.010
0.197
L mm 0.40
1.27
in. 0.016
0.050
α 0° 8°
Rev. 1.0
July 2003
Page 11 of 11
11 Page |
Páginas | Total 11 Páginas | |
PDF Descargar | [ Datasheet FM25CL04.PDF ] |
Número de pieza | Descripción | Fabricantes |
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