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PDF FM25C640UV Data sheet ( Hoja de datos )

Número de pieza FM25C640UV
Descripción 64K-Bit SPI Interface Serial CMOS EEPROM
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FM25C640UV Hoja de datos, Descripción, Manual

February 2002
FM25C640U
64K-Bit SPI™ Interface
Serial CMOS EEPROM
General Description
The FM25C640U is a 64K bit serial interface CMOS EEPROM
(Electrically Erasable Programmable Read-Only Memory). This
device fully conforms to the SPI 4-wire protocol which uses Chip
Select (/CS), Clock (SCK), Data-in (SI) and Data-out (SO) pins to
synchronously control data transfer between the SPI microcontroller
and the EEPROM. In addition, the serial interface allows a minimal
pin count, packaging designed to simplify PC board layout re-
quirements and offers the designer a variety of low voltage and low
power options.
This SPI EEPROM family is designed to work with the 68HC11 or
any other SPI-compatible, high-speed microcontroller and offers
both hardware (/WP pin) and software ("block write") data protec-
tion. For example, entering a 2-bit code into the STATUS REGIS-
TER prevents programming in a selected block of memory and all
programming can be inhibited by connecting the /WP pin to VSS;
allowing the user to protect the entire array or a selected section.
In addition, SPI devices feature a /HOLD pin, which allows a
temporary interruption of the datastream into the EEPROM.
Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability, and low power con-
sumption for a continuously reliable non-volatile solution for all
markets.
Functions
I SPI MODE 0 interface
I 64K bits organized as 8K x 8
I Extended 2.7V to 5.5V operating voltage
I 2.1 MHz operation @ 4.5V - 5.5V
I Self-timed programming cycle
I "Programming complete" indicated by STATUS REGISTER
polling
I /WP pin and BLOCK WRITE protection
Features
I Sequential read of entire array
I 32 byte "Page write" mode to minimize total write time per
byte
I /WP pin and BLOCK WRITE protection to prevent inadvert-
ent programming as well as programming ENABLE and
DISABLE opcodes.
I /HOLD pin to suspend data transfer
I Typical 1µA standby current (ISB) for "L" devices and 0.1µA
standby current for "LZ" devices.
I Endurance: Up to 1,000,000 data changes
I Data retention greater than 40 years
Block Diagram
/CS
/HOLD
SCK
SI
Instruction
Register
Address
Counter/
Register
Decoder
Instruction
Decoder
Control Logic
and Clock
Generators
Program
Enable
VPP
High Voltage
Generator
and
Program
Timer
EEPROM Array
VCC
VSS
/WP
SPI™ is a trademark of Motorola Corporation
Read/Write Amps
Data In/Out Register
8 Bits
Non-Volatile
Status Register
Data Out
Buffer
SO
© 2002 Fairchild Semiconductor Corporation
FM25C640U Rev. B
1
www.fairchildsemi.com

1 page




FM25C640UV pdf
FIGURE 1. Synchronous Data Timing Diagram
/CS
Mode 3
SCK
Mode 0
SI
SO
tCSS
tCLH
tCLL
tCSH
tDIS tDIH
Valid Input
tPD tDH
Valid Output
tCSI
Mode 3
Mode 0
tDF
High Z
FIGURE 2. SPI Protocol
/CS
Mode 3
SCK
SI Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Don't Care
Mode 3
SO High Z
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FIGURE 3. HOLD Timing
CS
SCK
Low state ( /CS = 0)
tHDS tHDH
Don't Care
tHDS tHDH
/HOLD
SO Output (n+2)
SI Input (n+2)
Output (n+1)
tHZ
Output (n)
Input (n+1)
Input (n)
High Z
Don't Care
tLZ
Output (n)
tDIS
Input (n)
FM25C640U Rev. B
5 www.fairchildsemi.com

5 Page





FM25C640UV arduino
Physical Dimensions inches (millimeters) unless otherwise noted
95° ± 5°
0.009 - 0.015
(0.229 - 0.381)
0.373 - 0.400
(9.474 - 10.16)
0.092 DIA
(2.337)
Pin #1 IDENT
0.090
(2.286)
8765
+
0.280 MIN
(7.112)
0.300 - 0.320
(7.62 - 8.128)
Option 1
1234
0.040 Typ.
0.030 MAX (1.016)
(0.762) 20° ± 1°
0.250 - 0.005
(6.35 ± 0.127)
0.039
(0.991)
0.032 ± 0.005
(0.813 ± 0.127)
RAD
Pin #1
IDENT
87
1
Option 2
0.145 - 0.200
(3.683 - 5.080)
0.130 ± 0.005
(3.302 ± 0.127)
+0.040
0.325 -0.015
+1.016
8.255 -0.381
0.125
(3.175)
DIA
NOM
0.065
(1.651)
0.045 ± 0.015
(1.143 ± 0.381)
0.050
(1.270)
90° ± 4°
Typ
0.125 - 0.140
(3.175 - 3.556)
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.020
(0.508)
Min
0.060
(1.524)
Molded Dual-In-Line Package (N)
Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably ex-
pected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Americas
Customer Response Center
Tel. 1-888-522-5372
Fairchild Semiconductor
Europe
Fax: +44 (0) 1793-856858
Deutsch Tel: +49 (0) 8141-6102-0
English Tel: +44 (0) 1793-856856
Français Tel: +33 (0) 1-6930-3696
Italiano Tel: +39 (0) 2-249111-1
Fairchild Semiconductor
Hong Kong
8/F, Room 808, Empire Centre
68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
Fairchild Semiconductor
Japan Ltd.
4F, Natsume Bldg.
2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
FM25C640U Rev. B
11 www.fairchildsemi.com

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