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PDF FM18L08-70-S Data sheet ( Hoja de datos )
| Número de pieza | FM18L08-70-S | |
| Descripción | 256Kb 2.7-3.6V Bytewide FRAM Memory | |
| Fabricantes | ETC | |
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Preliminary
FM18L08
256Kb 2.7-3.6V Bytewide FRAM Memory
Features
256K bit Ferroelectric Nonvolatile RAM
• Organized as 32,768 x 8 bits
• 10 year data retention at 85° C
• Unlimited read/write cycles
• NoDelay™ write
• Advanced high-reliability ferroelectric process
Superior to Battery-backed SRAM
• No battery concerns
• Monolithic reliability
• True surface mount solution, no rework steps
• Superior for moisture, shock, and vibration
• Resistant to negative voltage undershoots
SRAM & EEPROM Compatible
• JEDEC 32Kx8 SRAM & EEPROM pinout
• 70 ns access time
• 130 ns cycle time
• Equal access & cycle time for reads and writes
Low Power Operation
• 2.7V to 3.6V operation
• 15 mA active current
• 15 µA standby current
Industry Standard Configuration
• Industrial temperature -40° C to +85° C
• 28-pin SOP or DIP
Description
The FM18L08 is a 256-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile but operates in other respects as a RAM.
It provides data retention for 10 years while
eliminating the reliability concerns, functional
disadvantages and system design complexities of
battery-backed SRAM. Fast-write time and practically
unlimited read/write endurance make it superior to
other types of nonvolatile memory and a good
substitute for ordinary SRAM.
In-system operation of the FM18L08 is very similar to
other RAM based devices. Memory read- and write-
cycles require equal times. The FRAM memory,
however, is nonvolatile due to its unique ferroelectric
memory process. Unlike BBSRAM, the FM18L08 is a
truly monolithic nonvolatile memory. It provides the
same functional benefits of a fast write without the
serious disadvantages associated with modules and
batteries or hybrid memory solutions.
These capabilities make the FM18L08 ideal for
nonvolatile memory applications requiring frequent or
rapid writes in a bytewide environment. The
availability of a true surface-mount package improves
the manufacturability of new designs, while the DIP
package facilitates simple design retrofits. The
FM18L08 offers guaranteed operation over an
industrial temperature range of -40°C to +85°C.
Pin Configuration
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
VDD
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
Ordering Information
FM18L08-70-S 70 ns access, 28-pin SOP
FM18L08-70-P 70 ns access, 28-pin DIP
This data sheet contains specifications for a product under development.
Ramtron International Corporation
Characterization is not complete; specifications may change without notice.
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000, Fax (719) 481-7058
www.ramtron.com
23 March 2001
1/11
1 page  
Ramtron
FRAM Design Considerations
When designing with FRAM for the first time, users
of SRAM will recognize a few minor differences. First,
bytewide FRAM memories latch each address on the
falling edge of chip enable. This allows the address
bus to change after starting the memory access. Since
every access latches the memory address on the
falling edge of /CE, users should not ground it as they
might with SRAM.
Users that are modifying existing designs to use
FRAM should examine the hardware address
decoders. Decoders should be modified to qualify
addresses with an address valid signal if they do not
Figure 2. Memory Address Relationships
FM18L08
already. In many cases, this is the only change
required. Systems that drive chip enable active, then
inactive for each valid address may need no
modifications. An example of the target signal
relationships are shown in Figure 2. Also shown is a
common SRAM signal relationship that will not work
for the FM18L08.
The main design issue is to create a decoder scheme
that will drive /CE active, then inactive for each
address. This accomplishes the two goals of latching
the new address and creating the precharge period.
FRAM
Signaling
CE
Address
Data
SRAM
Signaling
CE
Address
Valid Memory Read Relationship
A1
D1
A2
Invalid Memory Read Relationship
D2
A1 A2
Data
D1 D2
23 March 2001
5/11
5 Page 
Ramtron
28-pin 600-mil DIP
Index
Area
A1
D1
e
D
B1
FM18L08
E1
A2 A
E
eA
eB
Selected Dimensions
For complete dimensions and notes, refer to JEDEC MS-011
Controlling dimensions is in inches. Conversions to millimeters are
not exact.
Symbol
A
A1
A2
B
B1
D
D1
E
E1
e
eA
eB
Dim
in.
mm
in.
mm
in.
mm
in.
mm
in.
mm
in.
mm
in.
mm
in.
mm
in.
mm
in.
mm
in.
mm
in.
mm
Min
0.015
0.39
0.125
3.18
0.014
0.356
0.030
0.77
1.380
35.1
0.005
0.13
0.600
15.24
0.485
12.32
Nom.
Max
0.250
6.35
0.195
4.95
0.022
0.558
0.070
1.77
1.565
39.7
0.100 BSC
2.54 BSC
0.600 BSC
15.24 BSC
0.625
15.87
0.580
14.73
0.700
17.78
23 March 2001
11/11
11 Page | ||
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| PDF Descargar | [ Datasheet FM18L08-70-S.PDF ] | |
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