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PDF 100355F Data sheet ( Hoja de datos )
| Número de pieza | 100355F | |
| Descripción | Low Power Quad Multiplexer/Latch | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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August 1998
100355
Low Power Quad Multiplexer/Latch
General Description
The 100355 contains four transparent latches, each of which
can accept and store data from two sources. When both En-
able (En) inputs are LOW, the data that appears at an output
is controlled by the Select (Sn) inputs, as shown in the Oper-
ating Mode table. In addition to routing data from either D0 or
D1, the Select inputs can force the outputs LOW for the case
where the latch is transparent (both Enables are LOW) and
can steer a HIGH signal from either D0 or D1 to an output.
The Select inputs can be tied together for applications re-
quiring only that data be steered from either D0 or D1. A
positive-going signal on either Enable input latches the out-
puts. A HIGH signal on the Master Reset (MR) input over-
rides all the other inputs and forces the Q outputs LOW. All
inputs have 50 kΩ pulldown resistors.
Features
n Greater than 40% power reduction of the 100155
n 2000V ESD protection
n Pin/function compatible with 100155
n Voltage compensated operating range = −4.2V to −5.7V
n Standard Microcircuit Drawing
(SMD) 5962-9165401
Logic Symbol
Pin Names
E1, E2
S0, S1
MR
Dna– Dnd
Qa– Qd
Qa– Qd
Connection Diagrams
24-Pin DIP
DS100294-1
Description
Enable Inputs (Active LOW)
Select Inputs
Master Reset
Data Inputs
Data Outputs
Complementary Data Outputs
24-Pin Quad Cerpak
DS100294-2
© 1998 National Semiconductor Corporation DS100294
DS100294-3
www.national.com
1 page  
Military Version
AC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND
Symbol
Parameter
TC = −55˚C
Min Max
TC = +25˚C
Min Max
TC = +125˚C Units Conditions
Min Max
Notes
tPLH Propagation Delay
tPHL
Dna–Dnd to Output
(Transparent Mode)
0.40 2.30 0.50 2.20 0.50 2.60 ns
tPLH Propagation Delay
Figures 1, 2
tPHL
S0, S1 to Output
(Transparent Mode)
tPLH Propagation Delay
0.60 3.00 0.80 2.70 0.80 3.20 ns
0.50 2.60 0.60 2.30 0.70 2.70 ns
(Notes 8, 9,
10)
tPHL
E1, E2 to Output
tPLH Propagation Delay
0.60 2.80 0.70 2.60 0.70 2.90 ns Figures 1, 3 (Notes 8, 9,
tPHL MR to Output
10)
tTLH Transition Time
0.40 1.90 0.40 1.90 0.40 1.90 ns Figures 1, 2
(Note 11)
tTHL 20% to 80%, 80% to 20%
tS Setup Time
Dna– Dnd
0.90
0.90
0.90
ns Figure 4
(Note 11)
S0, S1
2.40
2.40
2.40
MR (Release Time)
1.50
1.50
1.50
Figure 3
tH
tpw (L)
tpw (H)
Hold Time
Dna– Dnd
S0, S1
Pulse Width LOW E1, E2
Pulse Width HIGH MR
0.40
0.00
2.00
2.00
0.40
0.00
2.00
2.00
0.40
0.00
2.00
2.00
ns Figure 4
ns Figure 2
ns Figure 3
(Note 11)
(Note 11)
(Note 11)
Note 8: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case
condition at cold temperatures.
Note 9: Screen tested 100% on each device at +25˚C, Temperature only, Subgroup A9.
Note 10: Sample tested (Method 5005, Table 1) on each Mfg. lot at +25˚, Subgroup A9, and at +125˚C, and −55˚C Temp., Subgroups A10 & A11.
Note 11: Not tested at +25˚C, +125˚C and −55˚C Temperature (design characterization data).
5 www.national.com
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 100355F.PDF ] | |
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