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PDF FIN1001M5 Data sheet ( Hoja de datos )

Número de pieza FIN1001M5
Descripción 3.3V LVDS 1-Bit High Speed Differential Driver
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FIN1001M5 Hoja de datos, Descripción, Manual

December 2001
Revised January 2002
FIN1001
3.3V LVDS 1-Bit High Speed Differential Driver
General Description
This single driver is designed for high speed interconnects
utilizing Low Voltage Differential Signaling (LVDS) technol-
ogy. The driver translates LVTTL signal levels to LVDS lev-
els with a typical differential output swing of 350 mV which
provides low EMI at ultra low power dissipation even at
high frequencies. This device is ideal for high speed trans-
fer of clock or data.
The FIN1001 can be paired with its companion receiver,
the FIN1002, or with any other LVDS receiver.
Features
I Greater than 600Mbs data rate
I 3.3V power supply operation
I 0.5ns maximum differential pulse skew
I 1.5ns maximum propagation delay
I Low power dissipation
I Power-Off protection
I Meets or exceeds the TIA/EIA-644 LVDS standard
I Flow-through pinout simplifies PCB layout
I 5-Lead SOT23 package saves space
Ordering Code:
Order Number
FIN1001M5
FIN1001M5X
Package Number
Package Description
MA05B
5-Lead SOT23, JEDEC MO-178, 1.6mm [250 Units on Tape and Reel]
MA05B
5-Lead SOT23, JEDEC MO-178, 1.6mm [3000 Units on Tape and Reel]
Pin Descriptions
Pin Name
DIN
DOUT+
DOUT
VCC
GND
NC
Description
LVTTL Data Input
Non-inverting LVDS Driver Output
Inverting LVDS Driver Output
Power Supply
Ground
No Connect
Connection Diagram
Pin Assignment for SOT23
Function Table
Input
DIN
L
H
H = HIGH Logic Level
Outputs
DOUT+
DOUT
LH
HL
L = LOW Logic Level
(Top View)
© 2002 Fairchild Semiconductor Corporation DS500721
www.fairchildsemi.com

1 page




FIN1001M5 pdf
DC / AC Typical Performance Curves (Continued)
FIGURE 10. Power Supply Current vs.
Frequency
FIGURE 11. Power Supply Current vs.
Power Supply Voltage
FIGURE 12. Power Supply Current vs.
Ambient Temperature
FIGURE 13. Differential Propagation Delay vs.
Power Supply
FIGURE 14. Differential Propagation Delay vs.
Ambient Temperature
FIGURE 15. Differential Pulse Skew (tPLH - tPHL) vs.
Power Supply Voltage
5 www.fairchildsemi.com

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