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PDF M24512 Data sheet ( Hoja de datos )
| Número de pieza | M24512 | |
| Descripción | 512 Kbit Serial IC Bus EEPROM | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M24512
512 Kbit Serial I²C Bus EEPROM
PRODUCT PREVIEW
s Compatible with I2C Extended Addressing
s Two Wire I2C Serial Interface
Supports 400 kHz Protocol
s Single Supply Voltage:
– 4.5V to 5.5V for M24512
– 2.5V to 5.5V for M24512-W
– 1.8V to 3.6V for M24512-R
s Hardware Write Control
s BYTE and PAGE WRITE (up to 128 Bytes)
s RANDOM and SEQUENTIAL READ Modes
s Self-Timed Programming Cycle
s Automatic Address Incrementing
s Enhanced ESD/Latch-Up Behaviour
s 100000 Erase/Write Cycles (minimum)
s 40 Year Data Retention (minimum)
DESCRIPTION
These I2C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are or-
ganised as 64Kx8 bits, and operate down to 2.5 V
(for the -W version), and down to 1.8 V (for the -R
version).
The and M24512 are available in Plastic Dual-in-
Line, Plastic Small Outline and Thin Shrink Small
Outline packages.
These memory devices are compatible with the
I2C extended memory standard. This is a two wire
Table 1. Signal Names
E0, E1, E2
Chip Enable Inputs
SDA
Serial Data/Address Input/
Output
SCL
Serial Clock
WC Write Control
VCC
Supply Voltage
VSS Ground
8
1
PSDIP8 (BN)
0.25 mm frame
16
1
SO16 (MJ)
300 mil width
Figure 1. Logic Diagram
VCC
3
E0-E2
SCL
WC
M24512
VSS
SDA
AI02275
September 1999
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/16
1 page  
Table 3. Device Select Code 1
Device Type Identifier
b7 b6 b5
Device Select Code
1
0
Note: 1. The most significant bit, b7, is sent first.
1
b4
0
M24512
Chip Enable
b3 b2 b1
E2 E1 E0
RW
b0
RW
The 8th bit is the RW bit. This is set to ‘1’ for read
and ‘0’ for write operations. If a match occurs on
the Device Select Code, the corresponding mem-
ory gives an acknowledgment on the SDA bus dur-
ing the 9th bit time. If the memory does not match
the Device Select Code, it deselects itself from the
bus, and goes into stand-by mode.
There are two modes both for read and write.
These are summarized in Table 6 and described
later. A communication between the master and
the slave is ended with a STOP condition.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta-
ble 4) is sent first, followed by the Least significant
Byte (Table 5). Bits b15 to b0 form the address of
the byte in memory.
Write Operations
Following a START condition the master sends a
Device Select Code with the RW bit set to ’0’, as
shown in Table 6. The memory acknowledges this,
and waits for two address bytes. The memory re-
sponds to each address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC=1 (during a period of time from the START
condition until the end of the two address bytes)
will not modify the memory contents, and the ac-
companying data bytes will not be acknowledged,
as shown in Figure 5.
Table 4. Most Significant Byte
b15 b14 b13 b12 b11 b10 b9
b8
Table 5. Least Significant Byte
b7 b6 b5 b4 b3 b2 b1 b0
Byte Write
In the Byte Write mode, after the Device Select
Code and the address bytes, the master sends
one data byte. If the addressed location is write
protected by the WC pin, the memory replies with
a NoAck, and the location is not modified. If, in-
stead, the WC pin has been held at 0, as shown in
Figure 6, the memory replies with an Ack. The
master terminates the transfer by generating a
STOP condition.
Page Write
The Page Write mode allows up to 128 bytes to be
written in a single write cycle, provided that they
are all located in the same ’row’ in the memory:
that is the most significant memory address bits
(b15-b7) are the same. If more bytes are sent than
will fit up to the end of the row, a condition known
as ‘roll-over’ occurs. Data starts to become over-
written (in a way not formally specified in this data
sheet).
The master sends from one up to 128 bytes of da-
ta, each of which is acknowledged by the memory
if the WC pin is low. If the WC pin is high, the con-
tents of the addressed memory location are not
modified, and each data byte is followed by a
Table 6. Operating Modes
Mode
RW bit
Current Address Read
1
Random Address Read
0
1
Sequential Read
1
Byte Write
0
Page Write
Note: 1. X = VIH or VIL.
0
WC 1
X
X
X
X
VIL
VIL
Bytes
1
1
≥1
1
≤ 128
Initial Sequence
START, Device Select, RW = ‘1’
START, Device Select, RW = ‘0’, Address
reSTART, Device Select, RW = ‘1’
Similar to Current or Random Address Read
START, Device Select, RW = ‘0’
START, Device Select, RW = ‘0’
5/16
5 Page 
M24512
Table 9. AC Characteristics
M24512
Symbol Alt.
Parameter
VCC=4.5 to 5.5 V VCC=2.5 to 5.5 V VCC=1.8 to 3.6 V
TA=0 to 70°C or TA=0 to 70°C or TA=0 to 70°C or Unit
–40 to 85°C
–40 to 85°C
–20 to 85°C4
Min Max Min Max Min Max
tCH1CH2
tR Clock Rise Time
300 300 1000 ns
tCL1CL2
tF Clock Fall Time
tDH1DH2 2 tR SDA Rise Time
300 300 300 ns
20 300 20 300 20 1000 ns
tDL1DL2 2
tF SDA Fall Time
20 300 20 300 20 300 ns
tCHDX 1 tSU:STA Clock High to Input Transition
600
600
4700
ns
tCHCL tHIGH Clock Pulse Width High
600
600
4000
ns
tDLCL tHD:STA Input Low to Clock Low (START)
600
600
4000
ns
tCLDX tHD:DAT Clock Low to Input Transition
0
0
0 µs
tCLCH tLOW Clock Pulse Width Low
1.3
1.3
4.7 µs
tDXCX
tSU:DAT
Input Transition to Clock
Transition
100
100
250 ns
tCHDH
tDHDL
tSU:STO Clock High to Input High (STOP)
tBUF
Input High to Input Low (Bus
Free)
600
1.3
600
4000
ns
1.3 4.7 µs
tCLQV 3
tAA Clock Low to Data Out Valid
200 900 200 900 200 3500 ns
tCLQX
tDH
Data Out Hold Time After Clock
Low
200
200
200 ns
fC fSCL Clock Frequency
400 400 100 kHz
tW tWR Write Time
10 10 10 ms
Note: 1. For a reSTART condition, or following a write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. This is preliminary data.
Table 10. AC Measurement Conditions
Input Rise and Fall Times
≤ 50 ns
Input Pulse Voltages
0.2VCC to 0.8VCC
Input and Output Timing
Reference Voltages
0.3VCC to 0.7VCC
Figure 9. AC Testing Input Output Waveforms
0.8VCC
0.7VCC
0.2VCC
0.3VCC
AI00825
11/16
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| PDF Descargar | [ Datasheet M24512.PDF ] | |
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