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PDF M2006-12A-622.0800 Data sheet ( Hoja de datos )

Número de pieza M2006-12A-622.0800
Descripción VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING
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Integrated
Circuit
Systems, Inc.
Product Data Sheet
M2006-12A
VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING
GENERAL DESCRIPTION
The M2006-12A is a VCSO (Voltage Controlled SAW
Oscillator) based clock generator
PLL designed for clock frequency
translation and jitter attenuation.
Clock multiplication ratios (including
forward and inverse FEC) are
pin-selected from pre-programming
look-up tables. Includes Hitless
Switching and Phase Build-out to
enable SONET (GR-253) / SDH (G.813) MTIE and
TDEV compliance during reference clock reselection.
Hitless Switching (HS) engages when a 4ns or greater
clock phase change is detected.
This phase-change triggered implementation of HS is
not recommended when using an unstable reference
(more than 1ns jitter pk-to-pk) or when the resulting
phase detector frequency is less than 5MHz.
PIN ASSIGNMENT (9 x 9 mm SMT)
FIN_SEL0
FEC_SEL0
FEC_SEL1
FEC_SEL2
FEC_SEL3
VCC
DNC
DNC
DNC
28 18
29 17
30 16
31 M 2 0 0 6 - 1 2 A 15
32 14
33 ( T o p V i e w ) 13
34 12
35 11
36 10
P0_SEL
P1_SEL
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
FEATURES
Reduced intrinsic output jitter and improved power
supply noise rejection compared to M2006-12
Similar to the M2006-02A - and pin-compatible - but
adds Hitless Switching and Phase Build-out functions
Includes APC pin for Phase Build-out function (for
absorption of the input phase change)
Pin-selectable PLL divider ratios support forward and
inverse FEC ratio translation
Input reference and VCSO frequencies up to 700MHz
(Specify VCSO frequency at time of order)
Low phase jitter of 0.25 ps rms typical
(12kHz to 20MHz or 50kHz to 80MHz)
Commercial and Industrial temperature grades
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
Figure 1: Pin Assignment
Example I/O Clock Combinations
Using M2006-12A-622.0800
PLL Ratio Input Clock (MHz) Output Clock (MHz)
1/1
237/255
(inverse FEC)
622.08, 155.52,
77.76, or 19.44
669.3266, 167.3316,
83.6658, or 20.9165
622.08
or
155.52
Table 1: Example I/O Clock Combinations Using M2006-12A-622.0800
Using M2006-12A-669.3266
PLL Ratio Input Clock (MHz) Output Clock (MHz)
237/255
(FEC rate)
1/1
622.08, 155.52,
77.76, or 19.44
669.3266, 167.3316,
83.6658, or 20.9165
669.3266
or
167.3316
Table 2: Example I/O Clock Combinations Using M2006-12A-669.3266
SIMPLIFIED BLOCK DIAGRAM
M2006-12A
Loop
Filter
APC
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_SEL
0
Rfec Div
1
VCSO
Mfec Div
Mfin Div
(1, 4, 8, or 32)
P0 Div
(1 or 4)
FOUT0
nFOUT0
4
FEC_SEL3:0
2
FIN_SEL1:0
Mfec / Rfec
Divider LUT
Mfin Divider
LUT
P1 Div
(1 or 4)
FOUT1
nFOUT1
P0_SEL
Figure 2: Simplified Block Diagram
P1_SEL
M2006-12A Datasheet Rev 1.0
Revised 28Jul2004
M2006-12A VCSO Based FEC Clock PLL with Hitless Switching
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400

1 page




M2006-12A-622.0800 pdf
Integrated
Circuit
Systems, Inc.
M2006-12A
VCSO BASED FEC CLOCK PLL WITH HITLESS
Automatic Phase Compensation (APC) Pin
The M2006-12A also includes a phase build-out
function that can be selectively enabled by asserting the
APC input (pin 25) to logic 1. The phase build-out
function works in conjunction with the HS function.
When the APC pin is asserted, the phase build-out
function enables the PLL to absorb most of the phase
change of the input clock which reduces re-lock time
and the generation of wander. (Wander is created in this
case by the generation of extra output clock cycles.)
When the APC pin is asserted, the phase build-out
function is triggered by same >4 ns phase transient (at
the phase detector) that triggers the HS function. Once
triggered, a new VCSO clock edge is selected for the
phase comparator feedback input. (The clock edge
selected is the one closest in phase to the new input
clock phase.) The residual phase detector phase error
following reselection is approximately 3-to-4 ns. The
narrow bandwidth selected by HS minimizes VCSO
drifting and switch transients during the process.
It is recommended that the APC pin remain low when
the phase detector frequency is less than 4 MHz.
Otherwise, the M2006-12A may have difficulty locking
to reference upon power-up.
Outputs
The M2006-12A provides a total of two differential
LVPECL output pairs: FOUT1 and FOUT0. Because each
output pair has its own P divider, the FOUT1 pair and the
FOUT0 can output the two different frequencies at the
same time. For example, FOUT1 can output 155.52MHz
while FOUT0 outputs 622.08MHz.
Any unused output should be left unconnected
(floating) in the system application. This will
minimize output switching current and therefore
minimize noise modulation of the VCSO.
External Loop Filter
To provide stable PLL operation, and thereby a low jitter
output clock, the M2006-12A requires the use of an
external loop filter. This is provided via the provided
filter pins (see Figure 4).
Due to the differential signal path design, the
implementation requires two identical complementary
RC filters as shown here.
RLOOP CLOOP
RPOST
RLOOP CLOOP
RPOST
CPOST
CPOST
OP_IN nOP_IN
49
OP_OUT nOP_OUT
85
Figure 4: External Loop Filter
nVC VC
67
See Example External Loop Filter Component Values table.
PLL bandwidth is affected by loop filter component
values, “Mfec” and “Mfin” values, and the “PLL Loop
Constants” listed in AC Characteristics on pg. 8.
The various “Non-FEC ratio” settings can be used to
actively change PLL loop bandwidth in a given
application. See “FEC PLL Ratio Dividers Look-up
Table (LUT)” on pg. 3.
PLL Simulator Tool Available
A free PC software utility is available on the ICS website
(www.icst.com). The M2000 Timing Modules PLL
Simulator is a downloadable application that simulates
PLL jitter and wander transfer characteristics. This
enables the user to set appropriate external loop
component values in a given application.
Go to the SAW PLL Simulator Software web page at
www.icst.com/products/calculators/m2000filterSWdesc.htm
Example External Loop Filter Component Values1
VCSO Parameters: KVCO = 800kHz/V, RIN = 50k, VCSO Bandwidth = 700kHz.
Device Configuration
Example External Loop Filter Component Values
FRef
(MHz)
FVCSO
(MHz)
FIN_SEL1:0
pins
FEC_ SEL3:0
pins
R loop
C loop
R post C post
Nominal Performance Using These Values
PLL Loop Damping Passband
Bandwidth Factor Peaking (dB)
19.44 622.08
0 0 1 1 0 0 11.5k2.2µF
34k470pF 1kHz
6.0 0.05
77.76
0 1 1110
155.52
1 0 1111
622.08
1 1 0 1 1 0 5.11k4.7µF
6.0 0.06
167.3317
1 0 0 0 0 1 113.0k0.22µF
6.0 0.06
669.3266
11
28.0k1.0µF
6.3 0.05
155.52 669.3266 1 0 1 0 0 1 121.0k0.22µF
6.0 0.05
622.08
1 1 30.1k1.0µF
6.5 0.05
Table 8: Example External Loop Filter Component Values
Note 1: KVCO , VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor, and
Passband Peaking. For PLL Simulator software, go to www.icst.com.
M2006-12A Datasheet Rev 1.0
5 of 10
Revised 28Jul2004
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400

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