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PDF M14C64 Data sheet ( Hoja de datos )
| Número de pieza | M14C64 | |
| Descripción | Memory Card IC 64/32 Kbit Serial IC Bus EEPROM | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M14C64
M14C32
Memory Card IC
64/32 Kbit Serial I²C Bus EEPROM
s Compatible with I2C Extended Addressing
s Two Wire I2C Serial Interface
Supports 400 kHz Protocol
s Single Supply Voltage (2.5 V to 5.5 V)
s Hardware Write Control
s BYTE and PAGE WRITE (up to 32 Bytes)
s BYTE, RANDOM and SEQUENTIAL READ
Modes
s Self-Timed Programming Cycle
s Automatic Address Incrementing
s Enhanced ESD/Latch-Up Behaviour
s 1 Million Erase/Write Cycles (minimum)
s 40 Year Data Retention (minimum)
s 5 ms Programming Time (typical)
DESCRIPTION
Each device is an electrically erasable program-
mable memory (EEPROM) fabricated with STMi-
croelectronics’s High Endurance, Single
Polysilicon, CMOS technology. This guarantees
an endurance typically well above one million
Erase/Write cycles, with a data retention of
40 years. The memory operates with a power sup-
ply as low as 2.5 V.
The M14C32 is available in wafer form (either
sawn or unsawn) and in micromodule form (on
film). The M14C64 is available in micro-module
Table 1. Signal Names
SDA
Serial Data/Address Input/
Output
SCL Serial Clock
WC Write Control
VCC
Supply Voltage
GND
Ground
Micromodule (D20)
Micromodule (D22)
Wafer
Figure 1. Logic Diagram
VCC
SCL
WC M14xxx
SDA
GND
AI02217
October 1999
1/14
1 page  
M14C64, M14C32
the seven bits are fixed at 1010000b (A0h), as
shown in Table 5.
The 8th bit is the read or write bit (RW). This bit is
set to ‘1’ for read and ‘0’ for write operations. If a
match occurs on the Device Select Code, the cor-
responding memory gives an acknowledgment on
the SDA bus during the 9th bit time. If the memory
does not match the Device Select code, it will de-
select itself from the bus, and go into stand-by
mode.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta-
ble 3) is sent first, followed by the Least significant
Byte (Table 4). Bits b15 to b0 form the address of
the byte in memory. Bits b15 to b13 are treated as
a Don’t Care bit on the M14C64 memory. Bits b15
to b12 are treated as Don’t Care bits on the
M14C32 memory.
Write Operations
Following a START condition the master sends a
Device Select code with the RW bit set to ’0’, as
Figure 6. Write Mode Sequences with WC=1
shown in Table 6. The memory acknowledges it
and waits for two bytes of address, which provides
access to the memory area. After receipt of each
byte address, the memory again responds with an
acknowledge and waits for the data byte. Writing
in the memory may be inhibited if input pin WC is
taken high.
Any write command with WC=1 (during a period of
time from the START condition until the end of the
two bytes address) will not modify the memory
content and will NOT be acknowledged on data
bytes, as shown in Figure 6.
Byte Write
In the Byte Write mode, after the Device Select
code and the address, the master sends one data
byte. If the addressed location is write protected by
the WC pin, the memory replies with a NoACK,
and the location is not modified. If, instead, the WC
pin has been held at 0, as shown in Figure 7, the
memory replies with an ACK. The master termi-
nates the transfer by generating a STOP condi-
tion.
WC
BYTE WRITE
ACK
ACK
ACK
NO ACK
DEV SEL
BYTE ADDR BYTE ADDR
DATA IN
R/W
WC
PAGE WRITE
WC (cont'd)
PAGE WRITE
(cont'd)
ACK
ACK
ACK
NO ACK
DEV SEL
BYTE ADDR BYTE ADDR DATA IN 1
DATA IN 2
R/W
NO ACK
NO ACK
DATA IN N
AI01120B
5/14
5 Page 
Figure 10. AC Waveforms
tCHCL
tCLCH
SCL
tDLCL
tDXCX
SDA IN
tCHDX
tCLDX
START
CONDITION
SDA
SDA
INPUT CHANGE
SCL
SDA OUT
tCLQV
DATA VALID
tCLQX
DATA OUTPUT
M14C64, M14C32
tCHDH
tDHDL
STOP &
BUS FREE
SCL
SDA IN
tCHDH
STOP
CONDITION
tW
WRITE CYCLE
tCHDX
START
CONDITION
AI00795B
Table 9. AC Measurement Conditions
Input Rise and Fall Times
≤ 50 ns
Input Pulse Voltages
0.2VCC to 0.8VCC
Input and Output Timing
Reference Voltages
0.3VCC to 0.7VCC
Figure 11. AC Testing Input Output Waveforms
0.8VCC
0.7VCC
0.2VCC
0.3VCC
AI00825
Table 10. Input Parameters1 (TA = 25 °C, f = 400 kHz)
Symbol
Parameter
Test Condition
CIN Input Capacitance (SDA)
CIN Input Capacitance (other pins)
tNS Low Pass Filter Input Time
Constant (SCL & SDA Inputs)
Note: 1. Sampled only, not 100% tested.
Min.
100
Max.
8
6
400
Unit
pF
pF
ns
11/14
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| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet M14C64.PDF ] | |
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