PDF M12L16161A-7T Data sheet ( Hoja de datos )

Número de pieza	M12L16161A-7T
Descripción	512K x 16Bit x 2Banks Synchronous DRAM
Fabricantes	ETC
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No Preview Available ! M12L16161A 512K x 16Bit x 2Banks Synchronous DRAM FEATURES z JEDEC standard 3.3V power supply z LVTTL compatible with multiplexed address z Dual banks operation z MRS cycle with address key programs GENERAL DESCRIPTION The M12L16161A is 16,777,216 bits synchro- nous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with high performance CMOS technology. Synchro- - CAS Latency (2 & 3 ) nous design allows precise cycle control with the - Burst Length (1, 2, 4, 8 & full page) use of system clock I/O transactions are possible - Burst Type (Sequential & Interleave) on every clock cycle. Range of operating fre- z All inputs are sampled at the positive going edge quencies, programmable burst length and pro- of the system clock z Burst Read Single-bit Write operation z DQM for masking z Auto & self refresh z 32ms refresh period (2K cycle) grammable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION Part NO. M12L16161A-4.3T M12L16161A-5T M12L16161A-5.5T M12L16161A-6T M12L16161A-7T M12L16161A-8T MAX Freq. 233MHz 200MHz 183MHz 166MHz 143MHz 125MHz Interface LVTTL Package 50 TSOP(II) PIN CONFIGURATION (TOP VIEW) VDD DQ0 DQ1 VSSQ DQ2 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ LDQM WE CAS RAS CS BA A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 VSS 49 DQ15 48 DQ14 47 VSSQ 46 DQ13 45 DQ12 44 VDDQ 43 DQ11 42 DQ10 41 VSSQ 40 DQ9 39 DQ8 38 VDDQ 37 N.C/RFU 36 UDQM 35 CLK 34 CKE 33 N.C 32 A9 31 A8 30 A7 29 A6 28 A5 27 A4 26 VSS 50PIN TSOP(II) (400mil x 825mil) (0.8 mm PIN PITCH) Elite Semiconductor Memory Technology Inc. P.1 Publication Date : Jan. 2000 Revision : 1.3u 1 page M12L16161A AC OPERATING TEST CONDITIONS (VDD=3.3V ± 0.3V,TA= 0 to 70 °C ) Parameter Value Input levels (Vih/Vil) 2.4 / 0.4 Input timing measurement reference level 1.4 Input rise and fall time tr / tf = 1 / 1 Output timing measurement reference level 1.4 Output load condition See Fig.2 Unit V V ns V Output 870 è 3.3V 1200 è VOH(DC) = 2.4V, IOH = -2mA VOL(DC) = 0.4V, IOL = 2mA 30 pF Output Z0=50 è Vtt =1.4V 50 è 30 pF (Fig.1) DC Output Load circuit (Fig.2) AC Output Load Circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Symbol Version -4.3 -5 -5.5 -6 -7 -8 tRRD(min) 8.6 10 11 12 14 16 tRCD(min) 12.9 15 16 16 16 20 Row precharge time tRP(min) 12.9 15 16 18 20 20 Row active time tRAS(min) 34.4 40 40 42 42 48 tRAS(max) 100 Row cycle time tRC(min) 47.3 55 60 60 63 68 Last data in to new col. Address delay tCDL(min) 1 Last data in to row precharge Last data in to burst stop tRDL(min) tBDL(min) 1 1 Col. Address to col. Address delay Number of valid output data tCCD(min) CAS latency=3 1 1 CAS latency=2 1 Unit ns ns ns ns us ns CLK CLK CLK CLK ea Note 1 1 1 1 1 2 2 2 3 4 Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 4. Minimum delay is required to complete write. 4. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks. Elite Semiconductor Memory Technology Inc. P.5 Publication Date : Jan. 2000 Revision : 1.3u 5 Page M12L16161A Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency=3, Burst Length=1 CLOCK CKE CS RAS CAS ADDR BA tC H 0 123 456 tCC Note1 tSH tRC D tCL tRAS tRC 7 8 9 10 11 12 13 14 15 16 17 18 19 HIGH tSH tSS tRP tSS tS H Ra tSS Note2 BS tSH tSS Ca Note2,3 BS tCCD tSS Cb tSH Note2,3 BS Cc Note2,3 Note4 BS BS Rb Note2 BS A10 /A P DQ WE DQM Ra Note 3 tRAC tSAC tSLZ Note 3 Note 3 *Note4 Qa tOH tSH Db tSS tS H tSS tSS tS H Rb Qc Row Active Read Write Read Precharge Row Active :Don't Care Elite Semiconductor Memory Technology Inc. P.11 Publication Date : Jan. 2000 Revision : 1.3u 11 Page

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