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PDF M1040-11-155.5200 Data sheet ( Hoja de datos )

Número de pieza M1040-11-155.5200
Descripción VCSO BASED CLOCK PLL WITH AUTOSWITCH
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No Preview Available ! M1040-11-155.5200 Hoja de datos, Descripción, Manual

Integrated
Circuit
Systems, Inc.
Preliminary Information
M1040
VCSO BASED CLOCK PLL WITH AUTOSWITCH
GENERAL DESCRIPTION
The M1040 is a VCSO (Voltage Controlled SAW
Oscillator) based clock generator
PLL designed for clock protection,
frequency translation and jitter
attenuation in OC-12/48 class optical
networking systems. It features dual
differential inputs with two modes of
input selection: manual and
automatic upon clock failure. The clock multiplication
ratios and output divider ratio are pin selectable. This
device provides two outputs. External loop components
allow the tailoring of PLL loop response.
FEATURES
Integrated SAW (surface acoustic wave) delay line;
low phase jitter of < 0.5ps rms, typical (12kHz to
20MHz)
Output frequencies of 62.5 to 175 MHz *; Two differen-
tial LVPECL outputs (CML, LVDS options available)
Loss of Lock (LOL) indicator output
Narrow Bandwidth control input (NBW pin);
Initialization (INIT) input overrides NBW at power-up
Dual reference clock inputs support LVDS, LVPECL,
LVCMOS, LVTTL
AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure; Hitless
Switching (HS), Phase Build-out (PBO) options enable
SONET (GR-253)/SDH (G.813) MTIE/TDEV compliance
Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
Industrial temperature available
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
SIMPLIFIED BLOCK DIAGRAM
M1040
NBW
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
INIT
LOL
3
MR_SEL2:0
MUX
0
1
0
1
Auto
Ref Sel
R Div
LOL
Phase
Detector
M / R Divider
LUT
PLL
Phase
Detector
M Divider
PIN ASSIGNMENT (9 x 9 mm SMT)
MR_SEL1
MR_SEL0
REF_ACK
LOL
NBW
VCC
DNC
DNC
DNC
28 18
29 17
30 16
31 M 1 0 4 0 15
32 14
33 ( T o p V i e w ) 13
34 12
35 11
36 10
P_SEL
INIT
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using M1040-11-155.5200
Input Reference
Clock (MHz)
PLL Ratio
(Pin Selectable)
Output Clock
(MHz)
(Pin Selectable)
19.44
77.76
155.52
622.08
8 155.52
2 or
1 77.76
0.25
Table 1: Example I/O Clock Frequency Combinations
* Specify VCSO center frequency at time of order.
Loop Filter
VCSO
P Divider
(1 or 2)
FOUT0
nFOUT0
FOUT1
nFOUT1
P_SEL
Figure 2: Simplified Block Diagram
M1040 Datasheet Rev 0.1
Revised 11Nov2003
M1040 VCSO Based Clock PLL with AutoSwitch
Integrated Circuit Systems, Inc. Communications Modules www.icst.com tel (508) 852-5400

1 page




M1040-11-155.5200 pdf
Integrated
Circuit
Systems, Inc.
PLL Operation
The M1040 is a complete clock PLL. It uses a phase
detector and configurable dividers to synchronize the
output of the VCSO with the selected reference clock.
The “M” divider divides the VCSO output frequency,
feeding the result into the plus input of the phase
detector. The output of the “R” divider is fed into the
minus input of the phase detector. The phase detector
compares its two inputs. The phase detector output,
filtered externally, causes the VCSO to increase or
decrease in speed as needed to phase- and
frequency-lock the VCSO to the reference input.
The value of the M divider directly affects closed loop
bandwidth.
The relationship between the nominal VCSO center
frequency (Fvcso), the M divider, the R divider, and the
input reference frequency (Fin) is:
Fvcso
=
Fin ×
M---
R
For the available M divider and R divider look-up table
combinations, Tables 3 and 4 on pg. 3 list the Total PLL
Ratio as well as Fin when using the M1040-11-155.5200.
(See “Ordering Information”, pg. 12.)
Due to the narrow tuning range of the VCSO
(+200ppm), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
Post-PLL Divider
The M1040 features a post-PLL (P) divider. By using
the P Divider, the device’s output frequency (Fout) can
be the VCSO center frequency (Fvcso) or 1/2 Fvcso.
The P_SEL pin selects the value for the P divider: logic 1
sets P to 2, logic 0 sets P to 1. (See Table 5 on pg. 6.)
When the P divider is included, the complete relation-
ship for the output frequency (Fout) is defined as:
Fout = --F----v---c---s---o---- = Fin × ------M-----------
P R× P
M1040
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Preliminary Information
Loss of Lock Indicator Output Pin
Under normal device operation, when the PLL is locked,
the LOL Phase Detector drives LOL to logic 0. Under
circumstances when the VCSO cannot lock to the input
(as measured by a greater than 4 ns discrepancy
between the feedback and reference clock rising edges
at the LOL Phase Detector) the LOL output goes to logic
1. The LOL pin will return back to logic 0 when the phase
detector error is less than 2 ns. The loss of lock
indicator is a low current LVCMOS output.
Guidelines Using LOL
As described, the LOL pin indicates when the PLL is
out-of-lock with the input reference. The LOL condition
is also used by the AutoSwitch circuit to detect a lost
reference, as described in following sections. LOL is
also used by the Hitless Switching and Phase Build-out
functions (optional device features). To ensure reliable
operation of LOL and guard against false out-of-lock
indications, the following conditions should be met:
The phase detector frequency should be no less than
5MHz, and preferably it should be 10MHz or greater.
Phase detector frequency is defined by Fin / R.
A higher phase detector frequency will result in lower
phase error and less chance of false triggering the
LOL phase detector. Refer to Tables 3 and 4 on pg. 3
for phase detector frequency when using the
M1040-11-155.5200.
The input reference should have an intrinsic jitter of
less than 1 ns pk-pk. If reference jitter is greater than
1 ns pk-pk, the LOL circuit might falsely trigger. Due
to this limitation, the LOL circuit should not be used in
loop timing mode, nor should it be used with a noisy
reference clock. Likewise, the AutoSwitch, Hitless
Switching, or Phase Build-out features should not be
used in loop timing mode or with a noisy reference
clock, since these features depend on LOL.
Reference Acknowledgement (REF_ACK) Output
The REF_ACK (reference acknowledgement) pin outputs
the value of the reference clock input that is routed to
the phase detector. Logic 1 indicates input pair 1
(nDIF_REF1, DIF_REF1); logic 0 indicates input pair 0
(nDIF_REF0, DIF_REF0). The REF_ACK indicator is an
LVCMOS output.
M1040 Datasheet Rev 0.1
5 of 12
Revised 11Nov2003
Integrated Circuit Systems, Inc. Communications Modules www.icst.com tel (508) 852-5400

5 Page





M1040-11-155.5200 arduino
Integrated
Circuit
Systems, Inc.
M1040
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Preliminary Information
ELECTRICAL SPECIFICATIONS (CONTINUED)
AC Characteristics
Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT = 150-175MHz,
LVPECL outputs terminated with 50to VCC - 2V
Symbol Parameter
Min Typ Max Unit Conditions
FIN Input Frequency
DIF_REF0, nDIF_REF0,
DIF_REF1, nDIF_REF1
15
700 MHz
FOUT
APR
PLL Loop
Constants 1
KVCO
RIN
Output Frequency
FOUT0, nFOUT0, FOUT1, nFOUT1
Absolute Pull-Range
of VCSO
VCO Gain
Commercial
Industrial
Wide Bandwidth
Internal Loop Resistor
Narrow Bandwidth
62.5
±120
±50
±200
±150
200
100
2100
175 MHz
ppm
ppm
kHz/V
k
k
BWVCSO VCSO Bandwidth
Φn
Phase Noise
and Jitter
J(t)
Single Side Band
Phase Noise
@155.52MHz
Jitter (rms)
@155.52MHz
1kHz Offset
10kHz Offset
100kHz Offset
12kHz to 20MHz
odc Output Duty Cycle 2
tR
Output Rise Time 2 for
FOUT0, nFOUT0, FOUT1, nFOUT1
tF
Output Fall Time 2 for
FOUT0, nFOUT0, FOUT1, nFOUT1
700
-72
-94
-123
0.4
45 50
350 450
kHz
dBc/Hz Fin=19.44_MHz
dBc/Hz Tot. PLL ratio =
dBc/Hz 8. See pg. 3
0.6 ps
55 %
550 ps
20% to 80%
350 450
550 ps
20% to 80%
Table 10: AC Characteristics
Note 1: Parameters needed for PLL Simulator software; see Table 6, Example External Loop Filter Component Values, on pg. 8.
Note 2: See Parameter Measurement Information on pg. 11.
PARAMETER MEASUREMENT INFORMATION
Input and Output Rise and Fall Time
Clock Inputs 20%
and Outputs
80%
tR
80%
VP-P
20%
tF
Figure 6: Input and Output Rise and Fall Time
Differential Input Level
VCC - 0.85
nDIF_CLK
VP-P
DIF_CLK
Cross Points
VCMR
Output Duty Cycle
nFOUT
FOUT
odc =
tPW
tPERIOD
tPW
(Output Pulse Width)
tPERIOD
Figure 8: Output Duty Cycle
+ 0.5
Figure 7: Differential Input Level
M1040 Datasheet Rev 0.1
11 of 12
Revised 11Nov2003
Integrated Circuit Systems, Inc. Communications Modules www.icst.com tel (508) 852-5400

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