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PDF M-986-2R2P Datasheet ( Hoja de datos )

Número de pieza M-986-2R2P
Descripción MFC Transceivers
Fabricantes Clare Inc. 
Logotipo Clare  Inc. Logotipo

Total 13 Páginas
		
M-986-2R2P Hoja de datos, Descripción, Manual
Features
Direct A-Law PCM digital input
2.048 Mb/s clocking
Programmable forward/backward mode
Programmable compelled/direct control
Operates with standard codecs for analog
interfacing
Microprocessor read/write interface
Binary or 2-of-6 data formats
Single- or dual-channel versions
5 volt power
Applications
Test equipment
Trunk adapters
Paging terminals
Traffic recorders
PBXs
Pin Assignments
Block Diagram
M-986-2R2
MFC Transceivers
Description
The M-986-1R2 and -2R2 MFC Transceivers contain
all the logic necessary to transmit and receive CCITT
R2F (forward) and R2B (backward) multifrequency
signals on one 40-pin integrated circuit (IC). M-986-
1R2 is a single-channel version; M-986-2R2 provides
two channels. R1 single and dual multifrequency
transceivers are also available as M-986-1R1 and -
2R1.
Operating with a 20.48 MHz crystal, the M-986 is
capable of providing a direct digital interface to an A-
law-encoded PCM digital input. Each channel can be
connected to an analog source using a coder-decoder
(codec) as shown in the Block Diagram below.
The M-986 can be configured by the customer to
operate with the transmitter and receiver either cou-
pled together or independently, allowing it to handle a
compelled cycle automatically or via command from
the host processor. For the R2 versions of the M-986,
A-law is used for coding/decoding. The M-986 is con-
figured and controlled through an integral coprocessor
port.
Ordering Information
Part #
M-986-1R2P
M-986-1R2PL
M-986-2R2P
M-986-2R2PL
Description
40-pin plastic DIP, Single Channel
44-pin PLCC, Single Channel
40-pin plastic DIP, Dual Channel
44-pin PLCC, Dual Channel
DS-M976-2R2-R3
www.clare.com
1

1 page

M-986-2R2P pdf
M-986-2R2
External Clock Option: An external frequency source
can be used by injecting the frequency directly in
X2/CLKIN, with X1 left unconnected. The external fre-
quency injected must conform to the specifications list-
ed in the External Frequency specification Table on
page 7.
Flammability/Reliability Specifications
Reliability:
Flammability:
185 FITS failures/billion hours
Passes UL 94 V-0 tests
Signal Description
Signal
DIP
Pinout
PLCC
Pinout
I/O/Z
Description
Note: Please see the following definitions: DIP = Dual In-line Package PLCC = Plastic Leaded Chip Carrier
D15-D8
18-11
13-17, 19-21
I/O/Z Unused. Leave open.
D7-D0
19-26
22-28, 30
I/O/Z 8-bit coprocessor latch.
TBLF
40
44
O Transmit buffer latch full flag.
RBLE
1
2
O Receive buffer latch empty flag
HI/LO
2
3
I Latch byte select pin. Tie low.
BIO 9 10 I Unused. Leave open.
RD 32 36 I/O Used by the external processor to read from the coprocessor
latch by driving the RD line active (low), thus enabling the output
latch to drive the latched data. When the data has been read, the
external device must bring the RD line high.
EXINT
5
6
I Unused. Leave open.
MC 3 4 I Microcomputer mode select pin. Tie low.
MC/PM
27
31
I Coprocessor mode select pin. Tie low.
RS 4 5
I Reset input for initializing the device. When an active low is placed
on RS pin for a minimum of five clock cycles, RD and WR are
forced high, and the data bus (D7 through D0) goes to a high
impedance state. The serial port clock and transmit outputs also go
to the high impedance state.
WR 31 35 I/O Used by the external processor to write data to the coprocessor
port. To write data the external processor drives the WR line low,
places data on the data bus, and then drives the WR line high to
clock the data into the on-chip latch.
XF 28 32
O Watchdog signal. Toggles at least once every 15 milliseconds when
the processor is functioning properly. If the pin is not toggled at
least once every 15 ms, the processor is lost and should be reset.
CLKOUT
6
7
O System clock output (one-fourth crystal/CLKIN frequency,
nominally 5.12 MHz).
VCC 30 34
I 5V supply pin.
VSS
10 1, 12, 18, 29
I Ground pin.
X1 7 8 O Crystal output pin for internal oscillator. If an internal oscillator is
not used, this pin should be left unconnected.
X2/CLKIN
8
9
I Input pin to the internal oscillator (X2) from the crystal.
Alternatively, an input pin for the external oscillator (CLKIN).
DR1 & DR0
33 & 29
37, 33
I Serial-port receive-channel inputs. 2.048 MHz serial data is received
in the receive registers via these pins. DR0 = channel 1; DR1 =
channel 2
DX1 & DX0
36 & 35
40, 39
O Serial-port transmit-channel outputs. 2.048 MHz serial data is
transmitted from the transmit registers on these pins.These outputs
are in the high-impedance state when not transmitting.
Rev. 3 www.clare.com
5

5 Page

M-986-2R2P arduino
M-986 Dual Channel 4-Wire Interface Circuit
M-986-2R2
Rev. 3 www.clare.com
11

11 Page


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