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PDF M-986-2A1P Datasheet ( Hoja de datos )

Número de pieza M-986-2A1P
Descripción MF Transceiver
Fabricantes Clare Inc. 
Logotipo Clare  Inc. Logotipo

Total 13 Páginas
		
M-986-2A1P Hoja de datos, Descripción, Manual
Features
Direct A-Law or µ-Law PCM digital input
2.048 Mb/s clocking
Operates with standard codecs for analog interfac-
ing
Microprocessor read/write interface
Binary or 2-of-6 data formats
Dual-channel
5 volt power
Applications
Test equipment
Trunk adapters
Paging terminals
Traffic recorders
PBXs
M-986-2A1
MF Transceiver
Description
The M-986-2A1 dual channel MF Transceiver con-
tains all the logic necessary to transmit and receive
(North American) CCITT Region 1 multifrequency
signals on one integrated circuit (IC).
Operating with a 20.48 MHz crystal, the M-986 is
capable of providing a direct digital interface to a m-
law or A-law encoded PCM digital input. Each channel
can be connected to an analog source using a coder-
decoder (codec) as shown in the Block Diagram
below.
The M-986 is configured and controlled through an
integral coprocessor port.
Ordering Information
Part #
M-986-2A1P
M-986-2A1PL
Description
40-pin plastic DIP
44-pin PLCC
Block Diagram
DS-M986-2A1
www.clare.com
1

1 page

M-986-2A1P pdf
Signal Description
Signal
D15-D8
D7-D0
TBLF
RBLE
HI/LO
BIO
RD
Pin
18-11
19-26
40
1
2
9
32
EXINT
MC
MC/PM
RS
5
3
27
4
I/O/Z
I/O/Z
I/O/Z
O
O
I
I
I/O
I
I
I
I
WR 31
XF 28
CLKOUT
VSS
VCC
X1
X2/CLKIN
DR1 & DR0
FR
6
10
30
7
8
33 & 29
37
DX1 & DX0
36 & 35
FSR 39
I/O
O
O
I
I
O
I
I
O
O
I
SCLK 34 I/O/Z
FSX 38
I
M-986-2A1
Description
Unused. Leave open.
8-bit coprocessor latch.
Transmit buffer latch full flag.
Receive buffer latch empty flag.
Latch byte select pin. Tie low.
Unused. Leave open.
Used by the external processor to read from the coprocessor latch by driving the
RD line active (low), thus enabling the output latch to drive the latched data.
When the data has been read, the external device must bring the RD line high.
Unused. Leave open.
Microcomputer mode select pin. Tie low.
Coprocessor mode select pin. Tie low.
Reset input for initializing the device. When an active low is placed on RS pin for
a minimum of five clock cycles, RD and WR are forced high, and the data bus
(LD7 through LD0) goes to a high impedance state. The serial port clock and
transmit outputs also go to the high impedance state.
Used by the external processor to write data to the coprocessor port. To write
data the external processor drives the WR line low, places data on the data bus,
and then drives the WR line high to clock the data into the on-chip latch.
Watchdog signal. Toggles at least once every 10 milliseconds when the
processor is functioning properly. If the pin is not toggled at least once every 10
ms, the processor is lost and should be reset.
System clock output (one-fourth crystal/CLKIN frequency, nominally 5.12 MHz).
Ground pin.
5V supply pin.
Crystal output pin for internal oscillator. If the internal oscillator is not used, this
pin should be left unconnected.
Input pin to the internal oscillator (X2) from the crystal. Alternatively, an input pin
for the external oscillator (CLKIN).
Serial-port receive-channel inputs. 2.048 MHz serial data is received in the receive
registers via these pins. DR0 = channel 1; DR1 = channel 2.
8 kHz internal serial-port framing output. If internal clocking is selected,
serial-port transmit and receive operations occur simultaneously on an active
(high) FR framing pulse.
Serial-port transmit-channel outputs. 2.048 MHz serial data is transmitted from
the transmit registers on these pins. These outputs are in the high-impedance
state when not transmitting. DX0 = channel 1; DX1 = channel 2.
8 kHz external serial-port receive-framing input. If external clocking is selected,
data is received via the receive pins (DR1 and DR0) on the active (low) FSR input.
The falling edge of FSR initiates the receive process, and the rising edge causes
the M-986 to process the data.
2.048 MHz serial-port clock. Master clock for transmitting and receiving serial-
port data. Configured as an input in external clocking mode or output in internal
clocking mode. Reset (RS) forces SCLK to the high-impedance state.
8 kHz external serial-port transmit-framing input. If external clocking is enabled,
data is transmitted on the transmit pins (DX1, DX0) on the active (low) input. The
falling edge of FSX initiates the transmit process, and the rising edge causes the
M-986 to internally load data for the next cycle.
Rev. 3 www.clare.com
5

5 Page

M-986-2A1P arduino
M-986 Dual Channel 4-Wire Interface Application Circuit
M-986-2A1
Rev. 3 www.clare.com
11

11 Page


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