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PDF 4069UB Data sheet ( Hoja de datos )
| Número de pieza | 4069UB | |
| Descripción | Hex Inverter | |
| Fabricantes | ON Semiconductor | |
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MC14069UB
Hex Inverter
The MC14069UB hex inverter is constructed with MOS P–channel
and N–channel enhancement mode devices in a single monolithic
structure. These inverters find primary use where low power
dissipation and/or high noise immunity is desired. Each of the six
inverters is a single stage to minimize propagation delays.
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
• Triple Diode Protection on All Inputs
• Pin–for–Pin Replacement for CD4069UB
• Meets JEDEC UB Specifications
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
– 0.5 to +18.0
– 0.5 to VDD + 0.5
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10
Unit
V
V
mA
PD Power Dissipation,
per Package (Note 3.)
500 mW
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8–Second Soldering)
– 55 to +125
– 65 to +150
260
°C
°C
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v vhigh–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
PDIP–14
P SUFFIX
CASE 646
SOIC–14
D SUFFIX
CASE 751A
TSSOP–14
DT SUFFIX
CASE 948G
MARKING
DIAGRAMS
14
MC14069UBCP
AWLYYWW
1
14
14069U
AWLYWW
1
14
14
069U
ALYW
SOEIAJ–14
F SUFFIX
CASE 965
1
14
MC14069U
AWLYWW
1
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14069UBCP PDIP–14
2000/Box
MC14069UBD
SOIC–14
2750/Box
MC14069UBDR2 SOIC–14 2500/Tape & Reel
MC14069UBDT TSSOP–14
96/Rail
MC14069UBDTEL TSSOP–14 2000/Tape & Reel
MC14069UBDTR2 TSSOP–14 2500/Tape & Reel
MC14069UBF SOEIAJ–14 See Note 1.
MC14069UBFEL SOEIAJ–14 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14069UB/D
1 page  
MC14069UB
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
–A–
14
1
G
8
–B– P 7 PL
0.25 (0.010) M B M
7
C R X 45 _
F
–T–
SEATING
PLANE
D 14 PL
K
0.25 (0.010) M T B S A S
M
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC
0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
http://onsemi.com
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