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PDF 4030B Datasheet ( Hoja de datos )

Número de pieza 4030B
Descripción CMOS Quad Exclusive-OR Gate
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo

Total 7 Páginas
		
4030B Hoja de datos, Descripción, Manual
CD4030BMS
December 1992
CMOS Quad Exclusive-OR Gate
Features
Pinout
• High Voltage Type (20V Rating)
• Medium-Speed Operation
- tPHL, tPLH = 65ns (typ) at VDD = 10V, CL = 50pF
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current Of 1µA at 18V Over Full
Package-Temperature Range;
- 100nA at 18V and +25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
CD4030BMS
TOP VIEW
A1
B2
J=AB 3
K=CD 4
C5
D6
VSS 7
14 VDD
13 H
12 G
11 M = G H
10 L = E F
9F
8E
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Functional Diagram
Applications
• Even and Odd-Parity Generators and Checkers
• Logical Comparators
• Adders/Subtractors
• General Logic Functions
Description
The CD4030BMS types consist of four independent Exclu-
sive-OR gates. The CD4030BMS provides the system
designer with a means for direct implementation of the
Exclusive-OR function.
The CD4030BMS is supplied in these 14-lead outline pack-
ages:
Braze Seal DIP H4H
Frit Seal DIP
H1B
Ceramic Flatpack H3W
A1
B2
C5
6
D
E8
9
F
12
G
H 13
3J
4
K
10
L
11 M
J=AB
M=GH
K=CD
L=EF
VSS = 7
VDD = 14
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-317
File Number 3305

1 page

4030B pdf
Specifications CD4030BMS
TABLE 6. APPLICABLE SUBGROUPS (Continued)
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
FUNCTION
Static Burn-In 1
Note 1
OPEN
3, 4, 10, 11
GROUND
1, 2, 5 - 9, 12, 13
VDD
14
9V ± -0.5V
OSCILLATOR
50kHz
25kHz
Static Burn-In 2
Note 1
3, 4, 10, 11
7 1, 2, 5, 6, 8, 9,
12 - 14
Dynamic Burn-
In Note 1
-
7
14
3, 4, 10, 11
2, 6, 9, 13
1, 5, 8, 12
Irradiation
Note 2
3, 4, 10, 11
7 1, 2, 5, 6, 8, 9,
12 - 14
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
Schematic Diagram
VDD
B*
2(5, 9, 12)
p
n
A*
1(6, 8, 13)
VSS
VDD
p
n
n
p
VSS
*INPUTS PROTECTED
BY CMOS PROTECTION
NETWORK
VDD
p
p
n
p
J
3(4, 10, 11)
n
TRUTH TABLE FOR 1 OF 4
INDENTICAL GATES
A
0
1
0
1
1 = High Level
0 = Low Level
B
0
0
1
1
J
0
1
1
0
VDD VSS
VSS
FIGURE 1. 1 OF 4 IDENTICAL GATES
7-321

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