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PDF 100350QC Data sheet ( Hoja de datos )

Número de pieza 100350QC
Descripción Low Power Hex D-Type Latch
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! 100350QC Hoja de datos, Descripción, Manual

July 1988
Revised August 2000
100350
Low Power Hex D-Type Latch
General Description
The 100350 contains six D-type latches with true and com-
plement outputs, a pair of common Enables (Ea and Eb),
and a common Master Reset (MR). A Q output follows its D
input when both Ea and Eb are LOW. When either Ea or Eb
(or both) are HIGH, a latch stores the last valid data
present on its D input before Ea or Eb went HIGH. The MR
input overrides all other inputs and makes the Q outputs
LOW. All inputs have 50 kpull-down resistors.
Features
s 20% power reduction of the 100150
s 2000V ESD protection
s Pin/function compatible with 100150
s Voltage compensated operating range = −4.2V to 5.7V
Ordering Code:
Order Number Package Number
Package Description
100350PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100350QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Devises also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP
Pin Descriptions
Pin Names
Description
D0D5
Ea, Eb
MR
Data Inputs
Common Enable Inputs (Active LOW)
Asynchronous Master Reset Input
Q0Q5
Q0Q5
Data Outputs
Complementary Data Outputs
© 2000 Fairchild Semiconductor Corporation DS009884
28-Pin PLCC
www.fairchildsemi.com

1 page




100350QC pdf
Switching Waveforms
FIGURE 2. Enable Timing
FIGURE 3. Reset Timing
Notes:
tS is the minimum time before the transition of the enable that information must be present at the data input.
tH is the minimum time after the transition of the enable that information must remain unchanged at the data input.
FIGURE 4. Data Setup and Hold Time
5
www.fairchildsemi.com

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