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PDF 3933 Data sheet ( Hoja de datos )

Número de pieza 3933
Descripción THREE-PHASE POWER MOSFET CONTROLLER
Fabricantes Allegro MicroSystems 
Logotipo Allegro MicroSystems Logotipo



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No Preview Available ! 3933 Hoja de datos, Descripción, Manual

3933
GHC 5
CC 6
GLB 7
SB 8
GHB 9
CB 10
GLA 11
SA 12
GHA 13
29 SENSE
28 RC
27 PWM
26 BRKSEL
25 BRKCAP
24 BRAKE
1293 DIR
22 H2
21 H3
Dwg. PP-068
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Supply Voltage, VBB ............................. 28 V
(peak) .............................................. 30 V
Terminal Voltage, VCCOUT ................. 13.2 V
(peak) .............................................. 15 V
Logic Input Voltage Range,
VIN .................. -0.3 V to VLCAP + 0.3 V
Sense Voltage Range,
VSENSE ............................. -5 V to VLCAP
Output Voltage Range,
VSA, VSB, VSC .................. -5 V to +30 V
VGHA, VGHB, VGHC . -5 V to VBB + 14 V
VCA, VCB, VCC ..................... VSX + 14 V
Operating Temperature Range,
TA ................................. -20°C to +85°C
Junction Temperature, TJ ................. +150°C
Storage Temperature Range,
TS ............................... -55°C to +150°C
THREE-PHASE POWER
MOSFET CONTROLLER
The A3933SEQ is a three-phase MOSFET controller for use with
bipolar brushless dc motors. It drives all n-channel external power
FETs, allowing system cost savings and minimizing r(DS)on power loss.
The high-side drive block is implemented with bootstrap capacitors at
each output to provide the floating positive supply for the gate drive.
The high-side circuitry also employs a unique “intelligent” FET
monitoring circuit that ensures the gate voltages are at the proper levels
before turn-on and during the ON cycle. This device is targeted for
applications with motor supplies from 12 V to 28 V.
Internal fixed off-time PWM current-control circuitry can be used to
regulate the maximum load current to a desired value. The peak load-
current limit is set by the user’s selection of an input reference voltage
and external sensing resistor. The fixed off-time pulse duration is set
by a user-selected external RC timing network.
A power-loss braking circuit brakes the motor on an under-voltage
condition. The device is configured to either coast or dynamically
brake the motor when this occurs.
The A3933SEQ is supplied in a 32-lead rectangular (9 x 7) plastic
chip carrier (quad pack) for minimum-area, surface-mount applica-
tions.
FEATURES AND BENEFITS
I Drives External N-Channel FETs
I Intelligent High-Side Gate Drive
I Selectable Coast or Dynamic Brake on Power Down
I Adjustable Dead Time for Cross-Conduction Protection
I Selectable Fast or Slow Current-Decay Modes
I Internal PWM Peak Current Control
I Reset/Coast Input
I 120° Hall Commutation with Internal Pullup
I Internal 5-V Regulator
I Low-Side Synchronous Rectification
I Direction Control
I PWM Speed-Control Input
I Fault-Diagnostic Output
I Under-Voltage Protection

1 page




3933 pdf
3933
THREE-PHASE POWER
MOSFET CONTROLLER
Terminal Descriptions
Terminal
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Name
PGND
RESET
GLC
SC
GHC
CC
GLB
SB
GHB
CB
GLA
SA
GHA
CA
VCCOUT
LCAP
FAULT
MODE
VBB
H1
H3
H2
DIR
BRAKE
BRKCAP
BRKSEL
PWM
RC
SENSE
REF
DEAD
AGND
RESET — A logic input used to enable the device, internally
pulled up to VLCAP (+5 V). A logic HIGH will disable the
device and force all gate drivers to 0 V, coasting the motor. A
logic LOW allows the gate drive to follow commutation logic.
This input overrides BRAKE.
GLA/GLB/GLC — Low-side, gate-drive outputs for external
NMOS drivers. External series-gate resistors (as close as
possible to the NMOS gate) can be used to control the slew rate
seen at the power-driver gate, thereby controlling the di/dt and
dv/dt of the SA/SB/SC outputs. Each output is designed and
specified to drive a 1000 pF load with a rise time of 50 ns.
SA/SB/SC — Directly connected to the motor, these terminals
sense the voltages switched across the load. These terminals
are also connected to the negative side of the bootstrap capaci-
tors and are the negative supply connections for the floating
high-side drive.
GHA/GHB/GHC — High-side, gate-drive outputs for external
NMOS drivers. External series-gate resistors (as close as
possible to the NMOS gate) can be used to control the slew rate
seen at the power-driver gate, thereby controlling the di/dt and
dv/dt of the SA/SB/SC outputs. Each output is designed and
specified to drive a 1000 pF load with a rise time of 100 ns.
CA/CB/CC — High-side connections for the bootstrap capaci-
tors, positive supply for high-side gate drive. The bootstrap
capacitor is charged to approximately VCCOUT when the
associated output SA/SB/SC terminal is low. When the output
swings high, the voltage on this terminal rises with the output to
provide the boosted gate voltage needed for n-channel power
FETs.
continued next page
www.allegromicro.com

5 Page





3933 arduino
3933
THREE-PHASE POWER
MOSFET CONTROLLER
0.33
0.54
13.86
12.10
LONG SIDE
(11.32
9.56
SHORT SIDE)
1.27
BSC
Dimensions in Millimeters
(for reference only)
20
21
0.66
0.82
15.11
14.86
14.04
13.90
29
0.38
MIN
3.18
3.55
30 32 1
11.50
11.36
12.57
12.32
14
13
5
4
Dwg. MA-006-32 mm
NOTES: 1. Lead spacing tolerance is non-cumulative.
2. Exact body and lead configuration at vendor’s option within limits shown
The products described here are manufactured under one or more U.S.
patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability
of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro products are not authorized for use as critical components in
life-support devices or systems without express written approval.
The information included herein is believed to be accurate and reliable.
However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which
may result from its use.
www.allegromicro.com

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